1993 Fiscal Year Final Research Report Summary
Fundamental studies on systolic arrays as a practical model of SIMD parallel computers
| Project/Area Number |
03680035
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
Informatics
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| Research Institution | OSAKA ELECTRO-COMMUNICATION UNIVERSITY |
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Principal Investigator |
UMEO Hiroshi OSAKA ELECTRO-COMMUNICATION UNIVERSITY, PROFESSOR, 工学部, 教授 (80132356)
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| Project Period (FY) |
1991 – 1993
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| Keywords | Parallel processing / Systolic array / Parallel algorithms / Systolic algorithms / SIMD / Fault-tolerance |
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| Research Abstract |
In this study we investigated fundamental properties of systolic arrays as a practical model of SIMD massive parallel computers. Our main results are as follows :
(1) We study the computational power of global bus systems (GB, for short) augmented with a mesh-connected computer (MCC, for short). First we show the GB is a useful tool for designing optimum-tifme parallel algorithms for MCCs and for showing correctness of those algorithms once designed. We do this by giving some design examples which utilize the GB very efficiently. Secondly we give a fundamental technique for the elimination of GB's. As an application of the technique, we will show that a rich variety of GBs on one- and two-dimensional MCC's can be eliminated without any loss of time efficiency.
(2) We consider the famous classical problem called firing squad synchronization form a view point of fault tolerance in an SIMD computational environment. Let A be an array of n cells with p faulty regions such that n_i (〕SY.gtoreq.〔) m_i and n_i + m_i (〕SY.gtoreq.〔) p - i for any i, l(〕SY.ltoreq.〔) i (〕SY.ltoreq.〔) p, where n_i and m_i are the number of cells in i-th non-faulty and faulty regions. We can construct a fault-tolerant (2n - 2 + p)-step nearly optimum firing squad synchronization algorithm for A.
We have developed a simulator system for SIMD systolic computers on an MIMD parallel computer consisting of 256 transputers. The system can simulate any computation of a large class of systolic arrays and enables us to evaluate various design parameters of the systolic arrays. The system also gives much helpful information on a graphic display for the elimination of bottle neck and imbalance on algorithmic design.
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