1993 Fiscal Year Final Research Report Summary
Study on Architecture and Design Methdology of Asynchronous Processors
| Project/Area Number |
04452192
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
情報工学
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
NANYA Takashi Tokyo Institute of Technology, Faculty of Engineering, Professor, 工学部, 教授 (80143684)
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| Co-Investigator(Kenkyū-buntansha) |
TAKAHASHI Ryuichi Tokyo Institute of Technology, Faculty of Engineering, Research Assistant, 工学部, 助手 (30236335)
YONEDA Tomohiro Tokyo Institute of Technology, Faculty of Engineering, Associate Professor, 工学部, 助教授 (30182851)
FUJIWARA Eiji Tokyo Institute of Technology, Faculty of Engineering, Professor, 工学部, 教授 (20211526)
TOHMA Yoshihiro Tokyo Institute of Technology, Faculty of Engineering, Professor, 工学部, 教授 (50016317)
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| Project Period (FY) |
1992 – 1993
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| Keywords | asynchronous circuits / microprocessor / architecture / logic design / two-rail two-phase / delay models / transition causality / dependency graph |
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| Research Abstract |
1) We developed an efficient synthesis method for asynchronous control circuits based on dependency relations between atomic operations such as register transfers and arithmetic operations. In this method, a dependency graph which describes a circuit behavior is directly mapped to a description of the interconnection among primitive circuit elements.
2) We designed a quasi-delay-insensitive general-purpose 8-bit microprocessor chip TITAC,and implemented it as a CMOS gate array. The TITAC project seeks to demonstrate that a design methodology is readily available for fully asynchronous VLSI systems that work in practice. Through the design and implementation of TITAC,we established a library of building blocks for the design automation of asynchronous VLSI systems.
3) We analized stuck-at faults that cause illegal signal transitions in quasi-delay-insensitive ccircuits, and proposed a design for testability by enhancing the controllability and observability of signal transitions.
4) We first defined the transition causality of a self-timed implementation as a set of causal relations that hold among signal transitions on the primary input, primary output and the internal gates, and proposed a new self-timed implementation of Boolean functions. The resulting circuit achieves a maximum parallelism, and consequently, has a potential of operating at a highest possible average speed on the delay-insensitive circuit-environment model.
5) We developed a gate model and circuit structure for pulse-driven asynchronous circuits implemented with the use of Josephson junction devices, in which the binary information is presented by very short voltage pulses.
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