| Co-Investigator(Kenkyū-buntansha) |
SATO Taketoshi KOKUSAI ELECTRIC Co.Ltd., TOYAMA FACTORY,TOYAMA PROCESS TECHNOLOGY CENTER,RESEAR, 富山工場・富山プロセス技術センター, 研究員
NAKAMURA Naoto KOKUSAI ELECTRIC Co.Ltd., TOYAMA FACTORY,TOYAMA PROCESS TECHNOLOGY CENTER,RESEAR, 富山工場・富山プロセス技術センター, 研究員
KUROKAWA Harushige KOKUSAI ELECTRIC Co.Ltd., TOYAMA FACTORY,FACTORY SUPERINTENDENT, 富山工場, 工場長取締役
MATSUURA Takashi TOHOKU UNIVERSITY,RESEARCH INSTITUTE OF ELECTRICAL COMMUNICATION,ASSOCIATE PROFE, 電気通信研究所, 助教授 (60181690)
ONO Shoichi TOHOKU UNIVERSITY,EMERITUS PROFESSOR, 電気通信研究所, 名誉教授
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| Research Abstract |
Purpose of this study is to develop and to estabish novel CVD apparatus as an atomic layr epitaxy technology widely applied to Si extremely large scale integrated circuits. In this CVD,simple hydride gases, i.e.SiH_4 and GeH_4, are used as a reactant gas. In higher partial pressure range of the reactant gases (around a few Pa or a few hundreds Pa), adsorbed layr of the gases are formed, and then flash heating by the flash light shot results in the reaction of adsorbed molecules and single atomic layr epitaxy of Si and Ge. So far, we have developed flash heating CVD apparatus and have been realized the separation between adsorption and reaction of reactant gases. In this year, as the last year of the term, we have realized atomic layr growth of Si and Ge and an atomic layr superlattice structure of Si_1Ge_1. Finally, we have fabricated a double barrier resonant tunneling diode, and current peaks due to resonant tunneling effect were clearly observed in the current-voltage characteristic
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Concretely itemizing,
(1) concerning to control the crystal structure of the initial surface for atomic layr epitaxy, a dimer structure on Si (100) was clearly observed after exposing the surface to the air,
(2) single atomic layr epitaxy of Ge on Si surface was realized by using flash heating CVD at 275ﾟC,
(3) single atomic layr epitaxy of Si on Ge surface was realized by self-limiting thermal reaction of SiH_4 at 200-300ﾟC,
(4) we have fabricated resonant tunneling diode with single Ge quantum well sandwiched by double Si_1 Ge_1 superlattice barriers, which were formed by alternately depositing the single atomic layrs of Si and Ge as stated in (2) and (3). All the process during/after growth of the double barrier structure were done below 300ﾟC.Negative resistance characteristic, in which clear current peaks appeared at the bias voltages of -0.6 V and 0.7 V approximately assigned to the predicted value, was observed.
The success of this project supplies a key to atomic layr controlled process applied to device fabrication and we summarized this project. Less
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