1993 Fiscal Year Final Research Report Summary
Implementation of Fast, Low Latency 2D IIR Digital filters using Separate Computation of Semizero-State and Zero-Input Responses.
| Project/Area Number |
04650282
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
電子通信系統工学
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| Research Institution | Kanazawa University |
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Principal Investigator |
TAKEBE Tsuyoshi Kanazawa University Facult.of Tech.Professor, 工学部, 教授 (20019699)
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| Co-Investigator(Kenkyū-buntansha) |
MATSUMOTO ToYoji Kanazawa University Inform.Process.Center Lecturer, 総合情報処理センター, 講師 (20173908)
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| Project Period (FY) |
1992 – 1993
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| Keywords | 2-D Digital Filter / Image Processing / Multiprocessor / Signal Processor / Block Processing / Ring Connected / State Space Model |
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| Research Abstract |
This paper treats multiprocessor implementation of fast, low latency 2D digital filters using block processing. 2D data plane is partitioned into square regions and a ring connected multiprocessor system is used for inter-region parallel processing in vertical direction, each processor filtering each region. Vertical state variables are transfered from a processor to a processor. In a particular region, putting the bottom edge vertical state variables to be zeroes, semizerostate responses of state variables by the left edge horizontal state variables and the input data samples are computed, then complete responses of state variables at the upper and right edges and filter outputs of the region are computed. Computed vertical state variables are transferred from a processor to the next upper processor. The processing progresses in vertical direction, one region at one step. The algorithm results significant decrease in computation amount compared to the conventional block processing algorithm. The system can give high throughput and low latency.
First, the filters expressed by an unity state equation are treated. Inter-region parallel processing is also performed. Computation is load equally allotted to each processor so that the system works in high efficiency. The system was constructed with TI's C-40 signal processor simulator.
Secondly, the filters consisting of cascaded low-order sections are treated. the system has lower computation amount and higher achievable throughput than the former. These are confirmed by simulation using C-40 simulator.
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