1993 Fiscal Year Final Research Report Summary
Study on Neutron Damage Dynamics of Highly Integrated Semiconductor Devices
| Project/Area Number |
04680229
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
Nuclear engineering
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| Research Institution | Osaka University |
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Principal Investigator |
IIDA Toshiyuki Osaka University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (60115988)
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| Project Period (FY) |
1992 – 1993
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| Keywords | Highly Integrated Semiconduct or Device / Neutron Damage / Damage Mechanism / Memory Integrated Circuit / Soft Error / Bit Soft Error Cross Section / CMOS SRAM IC / Si(n, alpha)Mg Reaction |
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| Research Abstract |
In order to examine the fusion neutron induced soft-error on memory ICs, several kinds of CMOS SRAM ICs were irradiated around room temperature with 14MeV neutrons from OKTAVIAN.A special apparatus composed of some interface circuits and a computer was developed, and the pattern and rate of soft-error upsets on the ICs were measured in- situ during neutron irradiation. It was found that neutron reaction caused not multiple but single type soft-errors and the number of the soft-errors increased proportionally with neutron fluence. There was also a large difference in the soft-error upset rate between set (from 0 to 1) and reset (from 1 to 0) soft-errors for some kinds of ICs. Considering the cell population in a chip, we obtained the neutron susceptibility constant, i.e.bit soft-error cross section of 2-3X10^<-15>cm^2 for 16K and 64K bit CMOS SRAM ICs, and 6-9X10^<-14>cm^2 for 256K and 1Mbit ICs, respectively. From the date on the bit soft-error cross section for 1Mbit samples, a DT neutron induced soft-error seems to be caused by Si(n, alpha)Mg reaction in the critical region of approximately 5mumX5mumX500A in a memory cell. Also, all memory cells were controllable after neutron irradiation and no permanent damage was caused by neutron fluence irradiation below about 10^<12>n/cm^2.
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