| Research Abstract |
The purpose of this research project is to develop an ideal device structure for use in ultra-fast and ultra-high-density integrated circuits, i.e., metal-gate, high-permittivity gate-insulator, metal-substrate SOI CMOS LSI.The device structures were optimized by using advanced device simulator. It was revealed that the high-dopant-concentration under the source/drain region make it possible to suppress short-channel effects for sub-0.1mum-channel length devices. Furthermore, the excellent current drive of the device was obtained by employing around 10nm-SoI films with low-dopant-concentration and tantalum oxide as high-permittivity gate insulator. In order to achieve the highest current drive, it is essential to reduce parasitic resistance. Therefore, we proposed a new structure in which metal electrode contacts are made with the vertical side walls of source and drain.
As one of the high-performance LSI fabrication process technologies, silicon-capping silicidation technology for ultr
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a-low contact resistance metallization was established, resulting in 10^<-9> OMEGAcm^2, which is about two orders of magnitude lower than the value of conventional technology. This is almost identical to the theoretical limit of metal/Si contacts. Copper films were grown at low-kinetic-energy plasma process, and the control of ion-bombardment energy and the post-annealing treatment made it possible to form giant-grain copper, and then highly-reliable copper interconnect technology was established. The electro- and stress-migration life times of these Cu interconnects are three orders of magnitude larger than that of conventional Al interconnects. Total low-temperature processing (low-temperature gate oxidation, low-temperature silicon epitaxy, 450ﾟC annealing of ion-implanted layrs, low-temperature glass reflow for planarization, and so forth) was also established. We have succeeded for the first time in growing high-integrity gate oxide films at such a low temperature at 450ﾟC.
In SOI MOSFET's with 1V power supply, it is essential to adjust the threshold voltage based on the work function of a gate material. SOI MOSFETs were made with Ta as a gate material, whose Fermi level is located at the center of silicon band gap. It was experimentally shown that the threshold voltage of both n-type and p-type SOI MOSFET can be controlled by employing Ta as gate material. Less
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