• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to project page

1995 Fiscal Year Final Research Report Summary

Effective Design Methodology for Analog LSIs that Acquires and Reuses Design

Research Project

Project/Area Number 05452197
Research Category

Grant-in-Aid for General Scientific Research (B)

Allocation TypeSingle-year Grants
Research Field 電子デバイス・機器工学
Research InstitutionKYOTO UNIVERSITY

Principal Investigator

TAMARU Keikichi  Kyoto University, Graduate School of Engineering, Professor, 工学研究科, 教授 (10127102)

Co-Investigator(Kenkyū-buntansha) KOBAYASHI Kazutoshi  Kyoto University, Graduate School of Engineering, Instructor, 工学研究科, 助手 (70252476)
MOSHNYAGA Vasily  Kyoto University, Graduate School of Engineering, Lecturer, 工学研究科, 講師 (40243050)
ONODERA Hidetoshi  Kyoto University, Graduate School of Engineering, Associate Professor, 工学研究科, 助教授 (80160927)
Project Period (FY) 1993 – 1995
KeywordsReuse of Design Procedure / Analog LSI / Design Methodology of Analog LSI / Analog ASIC / Symbolic Layout / Knowledge Aquisition / Reuse of Design Knowledge / LSI Design System
Research Abstract

We have developed an efficient design method for Analog LSIs that utilizes design procedures which are automatically acquired from a design process of a designer. We have applied the design methodology to circuit design and layout design of analog LSIs, and verified the effectiveness experimentally.
Our achievements are summarized as follows.
1.Development of a circuit design method that acquires and reuses design procedures.
We have developed IDL (Interactive Design Language) for describing design procedures. The procedure can be reused for automatic design.
2.Development of a layout design method that acquires and reuses design procedures
The design procedure operated by a designer is stored. It is augmented with information required for generalization. Resulting procedure can be reused for generating layout under different set of parameters.
3.Development of a prototype design system GUIDE that store and reuses design procedures
The above two methods have been implemented into a prototype design system GUIDE.GUIDE system provide an interactive design environment for a designer. When he completes his desigh, his design procedure is captured in the form of IDL.It can be reused for automatic design.
4.Application of the design system
Two systems have been developed using GUIDE system. They are an automatic characterization system for LSI Libraries and a parameter extraction system of MOSFET models. Both systems are verified to be effective through the use in the development of actual LSIs.

  • Research Products

    (12 results)

All Other

All Publications (12 results)

  • [Publications] H. Onodera: "Compaction with Shape Optimization" Proc. IEEE CICC. 545-548 (1994)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] H. Onodera: "Model-Adaptable MOSFET Parameter Extraction Method Using a Common Intermediate Model" Proc. IEEE ASIC Conf.323-326 (1994)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] H. Onodera: "Development of Module Generators from Extracted Design Procedures-Application to Analog Device Generation-" IEICE Trans. Fundamentals. E78-A. 160-168 (1995)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] H. Onodera: "Compaction with Shape Optimization and its Application to Layout Recycling" IEICE Trans. Fundamentals. E78-A. 169-176 (1995)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] H. Onodera: "Model-Adaptable MOSFET Parameter Extraction System for MOSFET Models" IEICE Trans. Fundamentals. E78-A. 569-572 (1995)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 小野寺秀俊: "中間モデルを用いたモデル依存性の小さいMOSFETパラメータ抽出手法" 電子情報通信学会論文誌A. J78-A. 1133-1141 (1995)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] H.Onodera: "Compaction with Shape Optimization" Proc.IEEE CICC. 545-548 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] H.Onodera: "Model-Adaptable MOSFET Parameter Extraction Method Using a Common Intermediate Model" Proc.IEEE ASIC Conf.323-326 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] H.Onodera: "Development of Module Generators from Extracted Design Procedures-Application to Analog Device Generation-" IEICE Trans.Fundamentals. Vol.E78-A. 160-168 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] H.Onodera: "Compaction with Shape Optimization and its Application to Layout Recycling" IEICE Trans.Fundamentals. Vol.E78-A. 169-176 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] H.Onodera: "Model-Adaptable MOSFET Parameter Extraction System" IEICE Trans.Fundamentals. Vol.E78-A. 569-572 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] H.Onodera: "Model-Adaptable MOSFET Parameter Extraction Method Using a Common Intermediate Model" IEICE Trans.Fundamentals. Vol.J78-A. 1133-1141 (1995)

    • Description
      「研究成果報告書概要(欧文)」より

URL: 

Published: 1997-03-04   Modified: 2021-04-07  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi