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1994 Fiscal Year Final Research Report Summary

Basic Research on High-Speed Boolean Function Manipulator

Research Project

Project/Area Number 05452352
Research Category

Grant-in-Aid for General Scientific Research (B)

Allocation TypeSingle-year Grants
Research Field 計算機科学
Research InstitutionKYOTO UNIVERSITY

Principal Investigator

YAJIMA Shuzo  Kyoto University, Faculty of Engineering, Professor, 工学部, 教授 (20025901)

Co-Investigator(Kenkyū-buntansha) YASUOKA Kouichi  Kyoto University, Data Processing Center, Instructor, 大型計算機センター, 助手 (20230211)
OGINO Hiroyuki  Kyoto University, Faculty of Engineering, Staff, 工学部, 教務職員 (40144323)
TAKENAGA Yasuhiko  Kyoto University, Faculty of Engineering, Instructor, 工学部, 助手 (20236491)
HAMAGUCHI Kiyoharu  Kyoto University, Faculty of Engineering, Lecturer, 工学部, 講師 (80238055)
TAKAGI Naofumi  Nagoya University, Faculty of Engineering, Assoc.Professor, 工学部, 助教授 (10171422)
Project Period (FY) 1993 – 1994
KeywordsBoolean Function / Binary Decision Diagram / Boolean Function Manipulation / Computer Aided Logic Design / Prallel Algorithm / Computational Complexity / Content Addressable Memory / Combinatorial Problem
Research Abstract

We have carried out basic research on high-speed manipulation of Boolean functions based on binary decision diagrams.
1.Algorithms and Complexity of Manipulating Binary Decision Diagrams
We have propsed highly parallel algorithms for reduction and Booleam operations, which are basic Boolean function manipulation based on binary decision diagrams (BDDs), and clarified their computational complexity. On the expressive power of BDDs, we have defined the class of Boolean functions expressible by polynomial size BDDs and compared it with the classes based on Turing machines. We have also studied on the size of BDDs representing threshold functions.
2.High-Speed Boolean Function Manipulator
We have propsed and experimented a method using secondary memory to manipulate very large shared BDDs (SBDDs) which cannot be stored in the main memory. Breadth-first manipulation of SBDDs is adopted in this method. We have also developed a parallel method to manipulate SBDDs on content sddressable memories (CAMs). It seems that very high parallelism can be realized using CAMs.
3.Computer Aided Logic Design Based on Boolean Processing
We have applied Boolean function manipulation based on SBDDs to computer aided logic design, First, we proposed a method to generate compace test sequences for scan-based seaquential circuits. The second one is the application to the several state assignment methods for asynchronous sequential circuits. As an application for the problems not in the field of logic design, we have proposed some methods to solve combinatorial problems using Boolean processing.

  • Research Products

    (24 results)

All Other

All Publications (24 results)

  • [Publications] Shuzo YAJIMA: "Compaction of Test Sets for Combinational Circuits Based on Symbolic Fault Simulation" IEICE Trans.Inf.& Syst.E76-D. 1121-1127 (1993)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Kiyoharu HAMAGUCHI: "Compact Test Sequences for Scan-Based Sequential Circuits" IEICE Trans.Fundamentals. E76-A. 1676-1683 (1993)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Shuzo YAJIMA: "Minimum Single Transition-Time Assignments for Asynchronous Sequential Circuits Using BDD" 情報処理学会論文誌. 35. 352-357 (1994)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Yasuhiko TAKENAGA: "Computational Complexity of Manipulating Binary Decision Diagrams" IEICE Trans.Inf.& Syst.E77-D. 642-647 (1994)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Yasuhiko TAKENAGA: "On the Computational Power of Binary Decision Diagrams" IEICE Trans.Inf.& Syst.E77-D. 611-618 (1994)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Ichiro SEMBA: "Combinatorial Algorithms Using Boolean Processing" 情報処理学会論文誌. 35. 1661-1673 (1994)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Shuzo YAJIMA: "Minimum Dne-Shot State Assignment for Asynchronous Sequential Machines Using BDD" 情報処理学会論文誌. 35. 1888-1899 (1994)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 矢島 修三: "確率的符号化時間記号シュミレーションによるタイミングエラー確率の解析" 情報処理学会論文誌. 34. 1125-1133 (1993)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Shuzo YAJIMA: "Breadth-First Manipulation of Very Large Binary Decision Diagrams" Proceedings of the 1993 IEEE/ACM International Conference on Computer Aided Design. 48-55 (1993)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Kiyoharu HAMAGUCHI: "Tne Complexity of Optimal Variable Ordering Problems of Shared Binary Decision Diagrams" Proceedings of 4th International Symposium on Algorithms and Computation(ISAAC'93). 389-398 (1993)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Kiyoharu HAMAGUCHI: "Another Look at LTL Model Checking" Proceedings of Conference on Computer-Aided Verification. 415-427 (1993)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Kyasuhiko TAKENAGA: "On the Size of Ordered Binary Decision Diagrams Representing Threshold Functions" Proceedings of 5th International Symposium on Algorithms and Computation(ISAAC'94). 584-592 (1994)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Shuzo YAJIMA: "Analysis of Timing Error Probability Using Probabilistic Coded Time-Symbolic Simulation" Trans.Information Processing Society Japan. Vol.34, No.5. 1125-1133 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shuzo YAJIMA: "Compaction of Test Sets for Combinational Circuits Based on Symbolic Fault Simulation" IEICE Trans.Inf.& Syst. Vol.E76-D,No.9. 1121-1127 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Kiyoharu HAMAGUCHI: "Compact Test Sequences for Scan-Based Sequential Circuits" IEICE Trans.Fundamentals. Vol.E76-A,No.10. 1676-1683 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shuzo YAJIMA: "Minimum Single Transition-Time Assignments for Asynchronous Sequential Circuits Using BDD" Trans.Information Processing Society Japan. Vol.35, No.2. 352-357 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Yasuhiko TAKENAGA: "Computational Complexity of Manipulating Binary Decision Diagrams" IEICE Trans.Inf.&Syst. Vol.E77-D,No.6. 642-647 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Yasuhiko TAKENAGA: "On the Computational Power of Binary Decision Diagrams" IEICE Trans.Inf.& Syst. Vol.E77-D,No.6. 611-618 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Ichiro SEMBA: "Combinatorial Algorithms Using Bollean Processing" Trans.Information Processing Society Japan. Vol.35, No.9. 1661-1673 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shuzu YAJIA: "Minimum One-Shot State Assignment for Asynchronous Sequential Machines Using BDD" Trans.Information Processing Society Japan. Vol.35, No.9. 1888-1899 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shuzo YAJIMA: "Breadth-First Manipulation of Very Large Binary Decision Diagrams" Proceedings of the 1993 IEEE/ACM international Conference on Computer Aided Design. 48-55 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Kiyoharu HAMAGUCHI: "The Complexity of the Optimal Variable Ordering Problems of Shared Binary Decision Diagrams" Proceedings of 4th International Symposium on Algorithms and Computation. 389-398 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Kiyoharu HAMAGUCHI: "Another Look at LTL Model Checking" Proceedings of Conference on Computer-Aided Verification. 415-427 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Yasuhiko TAKENAGA: "On the Size of Ordered Binary Decision Diagrams Representing Threshold Functions" Proceedings of 5th International Symposium on Algorithms and Com-Putation. 584-592 (1994)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 1996-04-15  

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