1994 Fiscal Year Final Research Report Summary
Basic Research on High-Speed Boolean Function Manipulator
| Project/Area Number |
05452352
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機科学
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| Research Institution | KYOTO UNIVERSITY |
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Principal Investigator |
YAJIMA Shuzo Kyoto University, Faculty of Engineering, Professor, 工学部, 教授 (20025901)
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| Co-Investigator(Kenkyū-buntansha) |
YASUOKA Kouichi Kyoto University, Data Processing Center, Instructor, 大型計算機センター, 助手 (20230211)
OGINO Hiroyuki Kyoto University, Faculty of Engineering, Staff, 工学部, 教務職員 (40144323)
TAKENAGA Yasuhiko Kyoto University, Faculty of Engineering, Instructor, 工学部, 助手 (20236491)
HAMAGUCHI Kiyoharu Kyoto University, Faculty of Engineering, Lecturer, 工学部, 講師 (80238055)
TAKAGI Naofumi Nagoya University, Faculty of Engineering, Assoc.Professor, 工学部, 助教授 (10171422)
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| Project Period (FY) |
1993 – 1994
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| Keywords | Boolean Function / Binary Decision Diagram / Boolean Function Manipulation / Computer Aided Logic Design / Prallel Algorithm / Computational Complexity / Content Addressable Memory / Combinatorial Problem |
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| Research Abstract |
We have carried out basic research on high-speed manipulation of Boolean functions based on binary decision diagrams.
1.Algorithms and Complexity of Manipulating Binary Decision Diagrams
We have propsed highly parallel algorithms for reduction and Booleam operations, which are basic Boolean function manipulation based on binary decision diagrams (BDDs), and clarified their computational complexity. On the expressive power of BDDs, we have defined the class of Boolean functions expressible by polynomial size BDDs and compared it with the classes based on Turing machines. We have also studied on the size of BDDs representing threshold functions.
2.High-Speed Boolean Function Manipulator
We have propsed and experimented a method using secondary memory to manipulate very large shared BDDs (SBDDs) which cannot be stored in the main memory. Breadth-first manipulation of SBDDs is adopted in this method. We have also developed a parallel method to manipulate SBDDs on content sddressable memories (CAMs). It seems that very high parallelism can be realized using CAMs.
3.Computer Aided Logic Design Based on Boolean Processing
We have applied Boolean function manipulation based on SBDDs to computer aided logic design, First, we proposed a method to generate compace test sequences for scan-based seaquential circuits. The second one is the application to the several state assignment methods for asynchronous sequential circuits. As an application for the problems not in the field of logic design, we have proposed some methods to solve combinatorial problems using Boolean processing.
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