1994 Fiscal Year Final Research Report Summary
IC neuro chip with analog synapses for a correct reaction neural network
| Project/Area Number |
05555105
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| Research Category |
Grant-in-Aid for Developmental Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
System engineering
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| Research Institution | Tohoku University |
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Principal Investigator |
SAWADA Yasuji Research Institute of Electorical Communication, Tohoku University, Professor, 電気通信研究所, 教授 (80028133)
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| Co-Investigator(Kenkyū-buntansha) |
NAKAJIMA Koji Research Institute of Electorical Communication, Tohoku University, Associate Pr, 電気通信研究所, 助教授 (60125622)
MUROTA Jyunichi Research Institute of Electorical Communication, Tohoku University, Professor, 電気通信研究所, 教授 (70182144)
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| Project Period (FY) |
1993 – 1994
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| Keywords | Neuro Chip / Analog Memory / Boltzmann Machine / Integrated Circuit / Floating Gate / Learning Function / Silicon IC / Hebbian Learning |
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| Research Abstract |
We have fabricated a microchip of a neural circuit with pulse representation. The neuron output is a voltage pulse train. The synapse is a constant current source whose output is proportional to the duty ratio of neuron output. Membrane potential is charged by collection of synaptic currents through a RC circuit, providing an analog operation similar to the biological neural systems. We use a 4-bit SRAM as the memory for synaptic weights.
Then, we have fabricated a new type of analog memory (Switched Diffusion Analog Memory) with a floating gate witch is used as a key component to store synaptic weights for integrated artificial neural networks. The analog memory comprises a tunnel junction, a connection TFT,two capacitors, and a MOSFET.A small capacitance realized by use of poly-Si oxide film as the tunneling barrier together with the switching of the TFT improves linearity. The experimental result agrees with the theoretical estimation.
The last, we designed and fabricated a new analog DBM (Deterministic Boltzmann Machine learning) chip using SDAM.DBM learning circuit designed by Hebbian rule is suitable for integrated analog neuro-chip by use of SDAM which can be operated simultaneously for learning mode and retrieving mode.
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