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1994 Fiscal Year Final Research Report Summary

IC neuro chip with analog synapses for a correct reaction neural network

Research Project

Project/Area Number 05555105
Research Category

Grant-in-Aid for Developmental Scientific Research (B)

Allocation TypeSingle-year Grants
Research Field System engineering
Research InstitutionTohoku University

Principal Investigator

SAWADA Yasuji  Research Institute of Electorical Communication, Tohoku University, Professor, 電気通信研究所, 教授 (80028133)

Co-Investigator(Kenkyū-buntansha) NAKAJIMA Koji  Research Institute of Electorical Communication, Tohoku University, Associate Pr, 電気通信研究所, 助教授 (60125622)
MUROTA Jyunichi  Research Institute of Electorical Communication, Tohoku University, Professor, 電気通信研究所, 教授 (70182144)
Project Period (FY) 1993 – 1994
KeywordsNeuro Chip / Analog Memory / Boltzmann Machine / Integrated Circuit / Floating Gate / Learning Function / Silicon IC / Hebbian Learning
Research Abstract

We have fabricated a microchip of a neural circuit with pulse representation. The neuron output is a voltage pulse train. The synapse is a constant current source whose output is proportional to the duty ratio of neuron output. Membrane potential is charged by collection of synaptic currents through a RC circuit, providing an analog operation similar to the biological neural systems. We use a 4-bit SRAM as the memory for synaptic weights.
Then, we have fabricated a new type of analog memory (Switched Diffusion Analog Memory) with a floating gate witch is used as a key component to store synaptic weights for integrated artificial neural networks. The analog memory comprises a tunnel junction, a connection TFT,two capacitors, and a MOSFET.A small capacitance realized by use of poly-Si oxide film as the tunneling barrier together with the switching of the TFT improves linearity. The experimental result agrees with the theoretical estimation.
The last, we designed and fabricated a new analog DBM (Deterministic Boltzmann Machine learning) chip using SDAM.DBM learning circuit designed by Hebbian rule is suitable for integrated analog neuro-chip by use of SDAM which can be operated simultaneously for learning mode and retrieving mode.

  • Research Products

    (12 results)

All Other

All Publications (12 results)

  • [Publications] Y. Sawada: "A scaling theory of living state" Physica A. 204. 543-554 (1994)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Y. Mizugaki: "Implementation of superconducting synapse into a neuro-based analog-to-digital converter" Appl. Phys. Lett.65. 1712-1713 (1994)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] H. Won: "A Pulsating Neural Network" Extended Abstracts of the 1994 Int. Conf. on SSDM. 379-381 (1994)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Y. Mizugaki: "New Approach Implementation of Neural Circuits Using Superconductive Devices" Extended Abstracts of the 1994 Int. Conf. on SSDM. 364-366 (1994)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] S. Sato: "LSI Neural Chip of Pulse-Output Network with Programmable Synapse" IEICE Trans. ELECTRON.E78-C. 94-100 (1995)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] K. Nakajima: "Hardware Implementation of New Analog Memory for Neural Networks" IEICE Trans. ELECTRON.E78-C. 101-105 (1995)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Y.Sawada: "A scaling theory of living state" Physica A. 204. 543-554 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Y.Mizugaki: "Implementation of superconducting synapse into a neuro-based analog-to-digital converter" Appl.Phys.Lett.65. 1712-1713 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] H.Won: "A Pulsating Neural Network" Extended Abstracts of the 1994 Int.Conf.on SSDM. 379-381 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Y.Mizugaki: "New Approach Implementation of Neural Circuits Using Superconductive Devices" Extended Abstracts of the 1994 Int.Conf.on SSDM. 364-366 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] S.Sato: "LSI Neural Chip of Pulse-Output Network with Programmable Synapse" IEICE Trans.ELECTRON.E78-C. 94-100 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K.Nakajima: "Hardware Implementation of New Analog Memory for Neural Networks" IEICE Trans.ELECTRON.E78-C. 101-105 (1995)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 1996-04-15  

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