| Research Abstract |
In this research, we developed a logic synthesis system using EXOR gates.
1.Optimization of various AND-EXOR expressions
We considered five classes of AND-EXOR expressions : FPRM(Fixed Polarity Reed-Muller expression), KRO(Kronecker expression), PSDKRO(pseudo-Kronecker expression), GRM(Generalized Reed-Muller expression), and ESOP(EXOR sum-of-products expresion). ESOPs require the fewest products among these expressions, but the optimization is, difficult. We developed EXMIN2, a heuristic minimization program for ESOPs.For the ESOPs with small number of inputs, we can obtain an exact minimum ESOPs by using exhaustive methods. We obtained all the minimum ESOPs up to 5 variables. We also developed a simplification program using the results of exact minimum ESOPs. We also developed an exact minimization method for ESOPs using BDDs. This program is useful for the functions with up to n=6 variables.
GRM is a sub-class of ESOPs. We invented an easily testable realization for GRMs, and developed
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an exact minimization method for GRMs by using BDDs, and a heuristic simplification method using iterative improvement method.
FPRM is a sub-class of GRMs. We developed a method to obtain exact minimum FPRMs by using multi-terminal EXOR ternary decision diagrams, and successfully minimized the FPRMs with more than 90 inputs and many outputs.
PSDKRO in a sub-class of ESOPs. We developed a minimization program for PSDKROs by using ETDDs. This method is much faster than EXMIN2, and can be used as pre-processor for ESOP minimization algorithm.
2.Synthesis of multi-level logic networks using EXOR gates.
We developed a method to derive multi-level logic networks using AND,OR,EXOR and inverters. The design method first generates a Pseudo-Kronecker decision diagram(PKDDs)from given functions.Then, it generates multi-level logic networks consisting of AND,OR,EXOR and inverters. Finally, it simplifies the networks by using local transformation. Experimental results using MCNC benchmarks show that our method is suitable for the design of arithmetic networks. Less
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