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1994 Fiscal Year Final Research Report Summary

A study on VLSI layout methods based on meta-heuristics

Research Project

Project/Area Number 05680274
Research Category

Grant-in-Aid for General Scientific Research (C)

Allocation TypeSingle-year Grants
Research Field 計算機科学
Research InstitutionHIROSHIMA UNIVERSITY

Principal Investigator

WAKABAYASHI Shinichi  Hiroshima Univ., Fac.of Eng., Assoc.Prof., 工学部, 助教授 (50210860)

Co-Investigator(Kenkyū-buntansha) KOIDE Tetsushi  Hiroshima Univ., Fac.of Eng., Research Assoc., 工学部, 助手 (30243596)
YOSHIDA Noriyoshi  Hiroshima Univ., Fac.of Eng., Professor, 工学部, 教授 (60037728)
Project Period (FY) 1993 – 1994
KeywordsMeta-heuristics / VLSI / Layout design / Floorplan Design / Cell placement / Global routing / Channel routing / Genetic algorithm
Research Abstract

In this research, we have studied the VLSI layout design methods based on meta-heuristics. For all algorithms developed in this research, we have performed simulations experiments to show their effectiveness. Summaries of the research results are as follows.
1.Hypergraph partitioning algorithms : We have developed algorithms for the hypergraph partitioning problem, which is one of the fundamental problems in VLSI layout design. In the proposed algorithms, clustering of nodes is performed to get a good solution.
2.A floorplanning method based on topological constraint manipulation : For the floorplan design of VLSI chips, we have developed a floorplanning algorithm, in which topological constraints of block placement arre dynamically changed.
3.Cell placement algorithms : We have developed two cell placement algorithms, one of which is based on genetic algorithms, and the other is a timing-driven cell placement algorithm.
4.Global routing methods : We have developed two global routing methods for standard cell layouts, whose objective is to minimize both the channel density and the total wire length.
5.Over-the-cell channel routing methods : We have proposed new cell models for standard cell layout design with over-the-cell three-layr channel routing, and developed channel routing algorithms.

  • Research Products

    (12 results)

All Other

All Publications (12 results)

  • [Publications] Shin'ichi Wakabayashi: "Gate array placement based on mincut partitioning with path delay constraints" Proc. 1993 IEEE ISCAS. 3. 2059-2062 (1993)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Tetsushi Koide: "A new global routing algorithm for over-the-cell routing in standard cell layouts" Proc.Euro-DAC. 116-121 (1993)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Tetsushi Koide: "Three-layer channel routing for standard cells with column-dependent variable over-the-cell routing capacities" Proc.1994 IEEE CICC. 643-646 (1994)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Tetsushi Koide: "A floorplanning method with topological constraint manipulation" Proc.1994 IEEE ISCAS. 1. 165-168 (1994)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Yoko Kamidoi: "On three-way graph partitioning" Proc.1994 IEEE ISCAS. 5. 173-176 (1994)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Kazunori Isomoto: "A graph bisection algorithm based on subgraph migration" IEICE Trans.Fundamentals of Electnonics,Communications,and Computer Scierces. E77-A. 2039-2044 (1994)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Shin'ichi Wakabayashi: "Gate array placement based on mincut partitioning with path delay constraints" Proc.1993 IEEE ISCAS. Vol.3. 2059-2062 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Tetsushi Koide: "A new global routing algorithm for over-the-cell routing in standard cell layouts" Proc.Euro-DAC. 116-121 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Tetsushi Koide: "Three-layr channel routing for standard cells with column-dependent variable over-the-cell routing capacities" Proc IEEE 1994 CICC. 643-646 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Tetushi Koide: "A floorplanning method with topological constraint manipulation" Proc.1994 IEEE ISCAS. Vol.1. 165-168 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Yoko Kamidoi: "On three-way graph partitioning" Proc.1994 IEEE ISCAS. Vol.5. 173-176 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Kazunori Isomoto: "A graph bisection algorithm based on subgraph migration" IEICE Trans.Fundamentals. Vol.E77-A,No.12. 2039-2044 (1994)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 1996-04-15  

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