1994 Fiscal Year Final Research Report Summary
Study on Interconnection Networks Towards Realization of a Reconfigurable Parallel Computer
| Project/Area Number |
05680278
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機科学
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| Research Institution | Kyushu Institute of Technology |
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Principal Investigator |
SUEYOSHI Toshinori Dept.of Artificial Intelligence, Kyushu Institute of Technology, Asso.Prof., 情報工学部, 助教授 (00117136)
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| Co-Investigator(Kenkyū-buntansha) |
TANAKA Koichiro Center for Microelectronic Systems, Kyushu Institute of Technology, Res.Assist., マイクロ化総合技術センター, 助手 (40253570)
APDUHAN Bernady Dept.of Artificial Intelligence, Kyushu Institute of Technology, Res.Assist., 情報工学部, 助手 (60238714)
KUGA Morihiro Center for Microelectronic Systems, Kyushu Institute of Technology, Lecturer, マイクロ化総合技術センター, 講師 (80243989)
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| Project Period (FY) |
1993 – 1994
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| Keywords | Parallel computer / Interconnection network / Reconfigurable / FPGA / Processor array / Hard macro |
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| Research Abstract |
The following describe the results on the study of interconnection networks towards realization of a reconfigurable parallel computer which were achieved in accordance with the research project plan :
1.On the interconnection network of reconfigurable MIMD parallel computer, the points to realize diverse topologies were summarized and the configuration method of a reconfigurable interconnection network which can directly realize the desired topology were clarified.
2.Furthermore, the concept of reconfigurable SIMD parallel computer which can flexibly rearrange not only its interconnection network but also its processor array elements to adapt with the application were described. Likewise, its configuration method and fault tolerance ability were confirmed.
3.The mapping strategies to realize the desired reconfigurable parallel computer utilizing FPGA,were clarified. Moreover, we fonud out that the generation time has an adverse effect on the automatic generation of FPGA configuration data
… More
based on mapping algorithm. Consequently, we prepared a library of FPGA configuration data to reduce the time to reconfigure topologies.
4.In the process of preparing the above library, the problem of reducing the operation speed in high density implementation caused by wire delay which is dependent on the placement and routing procedures, and the difficulty of control have occurred. So, the idea to control the fluctuation of wire delay was necessary. Thus, a new high performance and high density implementation method was developed to support the preparation of the hard macro of several circuits which cannot be handled by commercial tools.
5.A prototype of reconfigurable SIMD parallel computer was developed and had proven to realize processor arrays of different architectures. Furthermore, it was confirmed that high density and high performance implementation can be achieved utilizing the above-mentioned method compared with commercial CAE tools. With these, an integrated development support environment was constructed to develop the potentials of reconfigurable parallel computers. Less
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Research Products
(12 results)
