1995 Fiscal Year Final Research Report Summary
New Architecture Microprocessor Based on High-Density Distributed Placement of Memory-Function-Merged Processing Units
| Project/Area Number |
06452209
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | Tohoku University |
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Principal Investigator |
KOTANI Koji Tohoku Univ., Fac. of Eng., Research Associate, 工学部, 助手 (20250699)
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| Co-Investigator(Kenkyū-buntansha) |
SHIBATA Tadashi Tohoku Univ., Fac. of Eng., Associate Professorociate Professor, 工学部, 助教授 (00187402)
OHMI Tadahiro Tohoku Univ., Fac. of Eng., Professor, 工学部, 教授 (20016463)
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| Project Period (FY) |
1994 – 1995
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| Keywords | flexware / Neuron-MOS / low power / high-speed multipler / high-precision processing |
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| Research Abstract |
We have studied the fundamental technologies to realize flexible and real-time response intelligent systems by a "New Hardware" architecture, which completely differs from Von Neumann type microprocessors. In the "New Hardware, "a bottle-neck-free ideal data flowing can be achieved by the distributed placement of memory-function-merged real-time-reconfigurable processing units and by an effective networking of them, resulting in the realization of real-time response. The "flexware, " which has a real-time reconfigurability, can be constructed with a very small number of elements by using high-functionality four-terminal devices, namely, Neuron-MOS transistors (vMOS). An hand-shake circuit for ultra-high speed self-timed operation of microprocessors has been successively designed using vMOS design with fewer elements than CMOS design. The newly developed "Clocked-vMOS" circuit scheme, in which a clock-controlled switch is attached to the floating gate of vMOS,increases the accuracy and
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the reliability of the circuits and also allows the realization of the subtraction function directly on the floating gate of vMOS.This new circuit technology merges the switched-capacitor technology and the vMOS technology. Low power circuit scheme for vMOS has been developed by applying the sense-amplifier technology. By combining all these new technologies, we have developed a low power A/D converter and a high speed multiplier circuit. The fabricated 4-b flash A/D converter test circuit only dissipates 1.2mW at the sampling frequency of 6MS/s, reducing the power consumption to less than 1/10 of the conventional A/D converters. We have shown by simulation that the 64-b multiplier having the newly-developed flash-summation mechanism can operate at the throughput of 3ns. The fabrication process accuracy required to realize high-functionality vMOS circuits were studied. Accuracy of the order of few percents is required for the main structural parameters of the device when it is aimed to handle 50-level multiple-valued variable in vMOS circuits. Less
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