1996 Fiscal Year Final Research Report Summary
Ultra-Highly-Parallel Arithmetic and Logic Circuits and Their Multiple-Valued Integration
| Project/Area Number |
06452386
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | Tohoku University, Graduate School of Information Sciences |
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Principal Investigator |
KAMEYAMA Michitaka Tohoku University, Graduate School of Information Sciences, Professor, 大学院情報科学研究科, 教授 (70124568)
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| Co-Investigator(Kenkyū-buntansha) |
HANYU Takahiro Tohoku University, Graduate School of Information Sciences, Associate Professor, 大学院情報科学研究科, 助教授 (40192702)
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| Project Period (FY) |
1994 – 1996
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| Keywords | Highly Parallel Arithmetic and Logic Circuit / Linear Digital Circuit / Reed-Muller Expansion / Critical-Path Minimization / Redundant Coding / Multiple-Valued Current-Mode Integrated Circuit / Low Power Multiple-Valued Integrated Circuit |
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| Research Abstract |
Highly parallel hardware algorithms based on new data representation and circuit technology are key issues to develop VLSI processors in deep submicron geometry. Local computability and parallelism are one of the most important factors to reduce the critical delay path which determines processor performance.
In this research project, multiple-valued redundant encoding method for parallel hardware algorithms were investigated together with the multiple-valued circuit technology. Our concept is that linearlity is fully utilized to make systematic design feasible. Linear combinational circuits are constructed by adders and coefficient multipliers over GF (p).
Let us assume that the specifications are given by symbol-level operations. A linear circuit for a unary operation can be always transformed to a highly parallel circuit whose output depends on only 2 input-digits by the matrix transformation called the similar transformation. If all representation matrices are equal each other in k-ar
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y operations, we can obtain consistent sparce matrices for K representation matrices. A symmetrical operation is such a class of operations. However, we cannot always linearize every k-ary specification. To solve the problem, we introduce multiplicated recundant symbols by assigning multiple-valued code vertices to one symbol. A sufficient condition for the symbol-level linearlity is derived to make the redundant multiple-valued code assignment.
Extension of the above design method is also discussed in a class of non-linear combinational circuits based on Reed-Muller expansion. If we can obtain a matrix representation of a combinational circuit with a formulation of the product of a constant matrix and variable vectors, design of a highly parallel circuit can be attributed to find a sparce constant matrix. Such class of the combinational circuits is more general, so it will be very useful for the design of practical k-ary operations such as an adder and a multiplier.
Another aspect of this research is low-power high performance multiple-valued integrated circuits. A new current-mode multiple-valued MOS integrated circuit is proposed with higher driving capability in comparison with the conventional binary and multiple-valued digital circuits. Moreover, an effective current-source control technique is found which leads to low-power high-speed multiple-valued threshold logic operations. This new circuit technology will be effectively employed for the highly parallel arithmetic and logic circuits developed in this project. Less
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