| Co-Investigator(Kenkyū-buntansha) |
ISHII Idaku University of Tokyo, Graduated School of Engineering Research Associate, 大学院・工学系研究科, 助手 (40282686)
KIYASU Senya University of Tokyo, Graduated School of Engineering Research Associate, 大学院・工学系研究科, 助手 (20234388)
FUJIMURA Sadao University of Tokyo, Graduated School of Engineering Professor, 大学院・工学系研究科, 教授 (30010961)
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| Research Abstract |
The aim of this research is to realize high speed visual information processing by integrating photo detectors and processing elements which are directly connected at each pixel, and we design such a chip, develop an application system with one chip vision, and realize high speed visual feedback.
In 1994 we performed (1) design of a fundamental architecture for the whole system, (2) design of a new processing element, (3) development of circuits surrounding vision chip and prediction of performance in the whole circuit, and (4) basic design of application system and software.
In 1995 we realized (1) design and test of software for developers, (2) improvement of the whole circuit which was developed in 1994, and (3) examination of the algorithms for application system.
In 1996 we performed (1) design and test of visual feedback system, (2) evaluation of performance in the application system, (3) test and improve of the processing element, (4) design and test of instruction control circuit, and (5) development of a language for one chip vision and its compiler.
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