1995 Fiscal Year Final Research Report Summary
Time/Frequency Transform Domain Mixed Mode Circuit Simulation System
| Project/Area Number |
06650441
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
System engineering
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| Research Institution | Shizuoka University |
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Principal Investigator |
ASAI Hideki Shizuoka Univ.Dept. of Systems Eng. Associate professor, 工学部, 助教授 (40175823)
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| Project Period (FY) |
1994 – 1995
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| Keywords | Transmission Lines / Circuit Simulator / Relaxation Techniques / Macro Model / Hardware Description / Hierarchica Decomposition / Multi-Level Simulation / Analog / Digital Mixed Circuit |
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| Research Abstract |
This report describes, first, a waveform relaxation-based coupled lossy transmission lines circuit simulator DESIRE3T+. First, the generalized mehtod of characteristics (GMC) is reviewed, which replaces lossy transmission lines with equivalent disjoint networks. Next, the generalized line delay window (GLDW) partitioning technique is proposed, which accelerates the transient analysis of transmission lines circuits. Furthermore, GMC model and GLDW technique are implemented in DESIRE3T+, and the performance is estimated.
Moreover, a multi-level simulator for analog/digital mixed circuits with behavioral models is prescnted. Analog circuits have been analyzed by the detailed circuit simulator such as Spice. Since the detailed circuit simulation is very compute-intensive, the necessity of simulating large and comples circuits has prompted the development of multi-level simulation with behavioral models. Our simulator has been developed based on SPLIT and enables to analyze all of the subcircuits in a body with the consideration of the coupling effect between subcircuits. This methodology aids the concurrent design of analog circuits and analog/digital mixed circuits.
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