1995 Fiscal Year Final Research Report Summary
次世代画像符号化技術の研究(プログラマブル・アクセラレータ方式の検討)
| Project/Area Number |
06805033
|
|---|
| Research Category |
Grant-in-Aid for General Scientific Research (C)
|
| Allocation Type | Single-year Grants |
|---|
| Research Field |
情報通信工学
|
|---|
| Research Institution | Shinshu University |
|---|
Principal Investigator |
IZAWA Yuuji Faculty of Engineering, Shinshu University Associate Professor, 工学部, 助教授 (70252062)
|
|---|
| Project Period (FY) |
1994 – 1995
|
| Keywords | Image coding / Subband coding / Entropy coding / PLD (Programmable Logic Device) / Realtime signal processing |
|---|
| Research Abstract |
We proposed an image coding scheme named "Programmable Accelerators" in 1993, which enables rapid spread of image transmission technology based on new algorithms. In this scheme, logic devices named PLD (Programmable Logic Device) are implemented in the decoder system, and decoding procedures. written by programming language "C" and HDL (Hardware Description Language) for PLD is transmitted from coder to decoder. PLDs work as accelerators which cooperate with CPU,and enables real-time decode processing.
The purpose of this research is to develop coder/decoder, and to prove the advantage of this system. In this study, we adopted this scheme to subband coding, which has advantages compared with other coding systems such as MPEG,because of compatibility between conventional TV system and high definition TV system namely Hi-Vision.
The specifications of the developed coding system are shown below.
(1)Input signal : 8bit, monochrome
(2)Image size : 320*200-160*100 (variable)
(3)Transmission : Max 8Mbps
(4)Frame rate : 1.1- (frames/sec)
(5)PC interface : ISA Bus
Performance estimations of this system are not finished yet. However, experimental results show that the proposed system has the ability of real-time transmission at 8Mbps.
We have plans to improve frame rate (to about 10 frames/sec) , by means of high-speed data transmission between PC and PLD using PCI bus interface.
|
