| Project/Area Number |
07248102
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| Research Category |
Grant-in-Aid for Scientific Research on Priority Areas
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| Allocation Type | Single-year Grants |
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| Research Institution | Tohoku University |
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Principal Investigator |
KAMEYAMA Michitaka Tohoku University, Graduate School of Information Sciences, Professor, 大学院・情報学研究科, 教授 (70124568)
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| Co-Investigator(Kenkyū-buntansha) |
TERADA Hiroaki Kochi University of Technology, Department of Inforamation Systems Engineering, Professor, 情報システム工学科, 教授 (80028985)
TAMARU Keikichi Kyoto University, Graduate School of Informatics, Professor, 大学院・工学研究科, 教授 (10127102)
YASUURA Hiroto Kyushu University, Graduate School of Information Sciences and Electrical Engineering, Professor, 大学院・システム情報科学研究科, 教授 (80135540)
HIGUCHI Tatsuo Tohoku University, Graduate School of Information Sciences, Professor, 大学院・情報学研究科, 教授 (20005317)
TOHMA Yoshihiro Tokyo Denki University, Department of Information & Communication Engineering, Professor, 工学部, 教授 (50016317)
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| Project Period (FY) |
1995 – 1998
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| Keywords | Logic-In-Memory VLSI / Current-Mode Multiple-Valued Integrated Circuits / Nueron MOS / Functional Memory / Self-Timed Urtra-Highlv-Parallel Architecture / Moving Picture Compression / Higher-Radix Arithmetic Circuits / Neural Network |
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| Research Abstract |
We proposed fundamental technologies which make possible many applications such as multimedia systems, highly-safe intelligent integrated systems and home service robots. In comarison with conventional technogies, the performance improvement sometimes becomes the order of hundred-times larger. The developed new-concepts are shown below :
(1) A new logic-in-memory VLSI architecture based on multiple-valued floating-gate pass logic is proposed to solve communication bottleneck between memory units and arithmetic logic units. Since multiple-valued pass transistor network is realized by multiple-valued threshold literal and pass switch functions, the logic-in-memory VLSI can be implemented easily with a very simplecircuit. The performance improvement will be about fifty times higher than the conventional circuit architecture. Multiple-valued current-mode circuit technology will be merged with the logic-in-memory architecture in near future. The application is a new FPGA architecture with bo
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ttleneck-free communication, and a power control technique on memory and, arithmetic and logic units.
(2) A design methodology for neuron MOS logic combined with CMOS logic is proposed. Also, a system design environment is developed based on Soft-Core processor and a low power system architecture Power-Pro for designing flexible architectures.
(3) A new functional memory architecture is developed for computing inside memory devices. Several LSIs suited for vector quantization have been fabricated, which can be applied to real-time image compression.
(4) A novel and unique ULSI system architecture based upon the data-driven parallel processing scheme and the self-timed super-pipelined hardware is established. ULSI chips realized by using 0.25 micron 4 ML technology can process video signal operations at 8.6 BOPS (1.2W@2.5V).
(5) A design methods of fault-tolerant neural networks are discussed. For mutually coupled neural networks. some multiplicated techniques are developed. For feedforward neural networks, the application of relearning makes the MTTF greatly improved.
(6) Design of a neural computer architecture for intelligent processing and its computer architecture are developed. Also, implementation methods of the fundamental software such as operating system and the middleware on semiconductor chips are investigated.
(7) Beyond-binary computing algorithms for addition. multiplication, division, CORDIC, real/complex arithmetic. etc. are developed. Their impacts on high-performance processor design are demonstrated using binary/multi-valued/set-valued logic LSI technologies.
(8) Smart image sensors for high-speed and low-power moving picture compression architecture are developed. It is demonstrated that the on-sensor image compression is particularly useful for these purposes through actual CMOS sensor LSI chip implementation. Less
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