1996 Fiscal Year Final Research Report Summary
Research on Wave Phenomena of Hot Electron at the Insulator Interface and Its Application to Functional Electron Devices
| Project/Area Number |
07455132
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | TOKYO INSTITUTE OF TECHNOLOGY |
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Principal Investigator |
ASADA Masahiro Tokyo Institute of Technology, Department of Electrical and Electronic Engineering, Associate Professor, 工学部, 助教授 (30167887)
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| Co-Investigator(Kenkyū-buntansha) |
WATANABE Masahiro Tokyo Institute of Technology, Research Center for Quantum Effect Electronics, A, 量子エレクトロニクス研究センター, 助教授 (00251637)
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| Project Period (FY) |
1995 – 1996
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| Keywords | metal-insulator superlattice / cobalt silicide / calcium fluoride / ion-beam epitaxy / quantum-effect devices / hot electron interference / quantum interference transistor / 量子干渉トランジスタ |
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| Research Abstract |
This research was done aiming at the observation of new quantum-size effect at the interfaces in metal-insulator multilayred heterstructures, which effect can be very little observed in conventional semiconductor heterostructures, and its application to functional electron devices. The results are summarized as follows.
Metal (CoSi_2) -insulator (CaF_2) ultrathin multilayred structures were grown on silicon substrate using low-temperature ion-beam epitaxial growth technique for the insulator and the two-step epitaxy of silicon and cobalt for the silicide metal. Using these strucures, a transistor composed of resonant tunneling emitter and electron interferometer was fabricated for the observation of quantum interference at the metal-insulator interface of hot electrons injected into the insulator conduction band. Multiple negative resistance which can be attributed to the interference of hot electrons was observed at the liquid nitrogen temperature. The observed characteristics were in reasonable agreement with theoretical expectation in terms of the voltage interval between the negative differential resistance and also with the circuit simulation results including parasitic elements. It is shown theoretically that the parasitic resistance and leak current considerably degrade the peak-to-valley ratio of the negative differential resistance. In order to suppress the influence of the parasitic resistance, the reduction of the in-plane device size using electron-beam lithography was proposed, and related fabrication process was established. According to this process, a small-size transistor was fabricated and the multiple negative differential resistance was observed at room temperature. For the leak current, which is the other factor degrading the transistor characteristics, several origins and their relation to fabrication process were discussed considering the size dependence of the device characteristics.
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