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1996 Fiscal Year Final Research Report Summary

Research on Performance Evaluation Technology for High-Performance Computer Systems

Research Project

Project/Area Number 07458063
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionKyushu University

Principal Investigator

YASUURA Hiroto  Kyushu Univ., Dept. of CSCE,Prof., 大学院・システム情報科学研究科, 教授 (80135540)

Co-Investigator(Kenkyū-buntansha) SAKIGUCHI Satoshi  ETL,Dept. of CS,Researcher, 電子技術総合研究所, 主任研究管
SAWADA Sunao  Kyushu Univ., Dept. of CSCE,Res. Associ., 大学院・システム情報科学研究科, 助手 (70235464)
IWAIHARA Mizuho  Kyushu Univ., Dept. of CSCE,Associ. Prof., 大学院・システム情報科学研究科, 助教授 (40253538)
MURAKAMI Kazuaki  Kyushu Univ., Dept. of CSCE,Associ. Prof., 大学院・システム情報科学研究科, 助教授 (10200263)
Project Period (FY) 1995 – 1996
KeywordsPerformance Evaluation / High-Performance Computer Systems / Parallel Computer Systems / System-On-Silicon / Performance Modeling / Performance Estimation / Computer Architecture / VLSI
Research Abstract

The purpose of this research is to develop a comprehensive technology for evaluating the performance, cost, and power consumption of high-performance computer systems. We have performed the following researches in particular.
(a) Comprehensive performance evaluation on the compiler and the architecture for high-end microprocessors.
(b) Developing and benchmarking the compiler, targetted for application-specific embedded microprocessors, which is enable to optimize the object-code according to the instruction-cache configurations.
(c) Developing a modeling methodology for estimating the performance, area cost, and power consumption for "system-on-silicon" class VLSI,and then establishing a platform for evaluating tradeoff among these factors.
(d) For parallel computer systems such as workstation-clusters and MPPs (Massively Parallel Processors) ;
・Development of performance estimation models,
・Study of quantitative evaluation index on scalability, and
・Correlation analysis of benchmark programs.

  • Research Products

    (12 results)

All Other

All Publications (12 results)

  • [Publications] 宮嶋浩志 他: "ハイパスカラ・プロセッサ・アーキテクチャー動作原理および性能評価-" 情報処理学会論文誌. 36. 1964-1975 (1995)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 関口智嗣 他: "定量的な並列システムのスケーラビリティ評価指標" 並列処理シンポジウム'96論文集. 235-242 (1996)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 坂田聡子 他: "ホモロジー解析プログラムを用いたワークステーションクラスタ,TMC CM-5,Intel Paragonの性能評価" 情報処理学会論文誌. 37. 1440-1450 (1996)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Tohru Ishihara,et al.: "Basic Experimentation on Accuracy of Power Estimation for CMOS VLSI Circuits" Proceedings of 1996 Internationational Symposium on Low Power Electronics and Design. 117-120 (1996)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 田中良夫 他: "並列アルゴリズムにおけるCollective通信の性能比較" 情報処理学会研究報告. HPC-62-4. (1996)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 宮嶋浩志 他: "高性能システム・オン・チップ構成法に関する性能評価" 情報処理学会研究報告. HPC-62-6. 33-38 (1996)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Hiroshi Miyajima et al.: ""Hyperscalar Processor Architecture-Principle of Operations and Performance Evaluation-"" Transactions of IPS Japan. vol.36, no.8. 1964-1975 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Satoshi Sekiguchi et al.: ""A Metrical Approach for Measuring the Scalability of Parallel Systems"" Proc. of 1996 IPSJ Joint Symposium on Parallel Processing. 235-242 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Satoko Sakata et al.: ""Performance Evaluation on a Work-station Cluster, TMC CM-5 and Intel Paragon Using a Parallel Homology Analysis Program"" Transactions of IPS Japan. vol.37, no.7. 1440-1450 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Tohru Ishihara, et al.: ""Basic Experimentation on Accuracy of Power Estimation for CMOS VLSI Circuits"" Proceedings of 1996 International Symposium on Low Power Electronics and Design. 117-120 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Yoshio Tanaka et al.: ""Comparison of Collective Communication Performance on Parallel Algorithms"" IPSJ Technical Report. HPC-62-4. (1996)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Hiroshi Miyajima et al.: ""Performance Evaluation on High-Performance System-On-Chip Architectures"" IPSJ Technical Report. HPC-62-6. (1996)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 1999-03-09  

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