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1996 Fiscal Year Final Research Report Summary

Code Optimazation Method Based on Computational Reordering for Programs Written in General Purpose Languages and its Application to DSP Compiler

Research Project

Project/Area Number 07650414
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field 情報通信工学
Research InstitutionTokyo Institute of Technology

Principal Investigator

NISHIHARA Akinori  Tokyo Institute of Technology, Center for Research and Development of Educational Technology, Professor, 教育工学開発センター, 教授 (90114884)

Co-Investigator(Kenkyū-buntansha) SUGINO Nobuhiko  Tokyo Institute of Technology, Department of Physical Electronics, Research Asso, 工学部, 助手 (60242286)
Project Period (FY) 1995 – 1996
KeywordsGeneral Purpose Language / Compiler / Precedence Relation / Scheduling / Code Generation / Code Optimization / Memory Access
Research Abstract

Almost all the programs are developed by help of general purpose computer languages and their compilers, now. The ordinary compilers usually generate program codes with strictly following the computational order written in the source programs. These compilers can generate efficient codes for ordinary computers and microprocessors, but, for the recent processors like digital signal processors (DSPs), codes generated under the same compiler techniques include many overhead generate highly efficient codes by computational codes, because of multiple arithmetic operation units or multi-stages pipeline in these processors. Therefore, the goal of this project is to realize a completely new compiler system for general purpose languages, which can generate highly efficient codes.
C language is employed for a general purpose language in this project, because it is widely accepted. A given source program written in C can be represented by a flow graph with precedence relation between variables. In the flow graph, fork and conjunction nodes are introduced with conditional/non-conditional branches and loops in a program. By these nodes, the flow graph is partitioned into several primitive blocks. For each primitive block, an order with less overhead codes is derived by a scheduling algorithm under the precedence relation. In order to reduce overhead codes due to branch instructions, a method to moe codes between primitive blocks is proposed.
The proposed alogorithms are applied to the C compiler for TMS320C30 (TI) and muPD77230 (NEC). By codes generated by this compiler for several examples with conditional branches and loops, the proposed methods are proved to be effective.
On the otherhand, in order to derive a highly efficient DSP codes, not only optimization in computational ordering but also that in memory access is very important. In this project, optimization methods for DSP memory addressing are also investigated.

  • Research Products

    (16 results)

All Other

All Publications (16 results)

  • [Publications] N.Sugino,S.Iimuro,and A.Nishihara: "DSP Code Optimization utilizing Memory Addressing Operation" IEICE Trans. Fundamentals. E79-A,8. 1217-1224 (1996)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] N.Sugino,H.Miyazaki,S.Iimuro,and A.Nishihara: "Improved Code Optimization Method Utilizing Memory Addressing Operation and its Application to DSP Compiler" Proceedings 1996 International Symposium on Circuits and Systems. 2. 249-252 (1996)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] N.Sugino,J.Vilasdechanon,K.Likit-Anurucks and A.Nishihara: "Computational Ordering of Adaptive Digital Network under Pipeline Constraints and its Application to DSP Compilers" Proc. Asia-Pacific Conference on Circuit and Systems. 101-104 (1996)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] N.Sugino,S.Yoshida,and A.Nishihara: "Code Optimization Method for DSPs with Multiple Memory Addressing Registers and its Application to Compilers" Proc. of the 1996 IEEE Region 10 Conference. 619-624 (1996)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 杉野暢彦,西原明法: "メモリアドレッシング最適化によるDSPコードの改善とそのコンパイラへの応用" 第11回ディジタル信号処理シンポジウム講演論文集. 693-698 (1996)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 杉野暢彦,吉田征一郎,西原明法: "複数アドレスレジスタについてのメモリアドレッシングの最適化一手法" 電子情報通信学会技術研究報告. CAS96-24. 59-66 (1996)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] N.Sugino, S.Iimuro, and A.Nishihara: "DSP Code Optimization utilizing Memory Addressing Operation" IEICE Trans.Fundamentals. E79-A-No.8. 1217-1224 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N.Sugino, S.Ohbi, and A.Nishihara: "DSP Compiler for Matrix and Vector Expressions with Automatic Computational Ordering" IEICE Trans.Fundamentals. E78-A-No.8. 989-995 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N.Sugino, H.Miyazaki, S.Iimuro, and A.Nishihara: "Improved Code Optimization Method Utilizing Memory Addressing Operation and its Application to DSP Compiler" Proceedings 1996 International Symposium on Circuits and Systems. 2. 249-252 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N.Sugino, J.Vilasdechanon, K.Likit-Anurucks and A.Nishihara: "Computational Ordering of Adaptive Digital Networks under Pipeline Constraints and its Application to DSP Compilers" Proc.Asia-Pacific Conference on Circuit and Systems. 101-104 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N.Sugino, S.Yoshida, and A.Nishihara: "Code Optimization Method for DSPs with Multiple Memory Addressing Registers and its Application to Compilers" Proc.of the 1996 IEEE Region 10 Conference. 619-624 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N.Sugino and A.Nishihara: "A Memory Addressing Optimization Method for DSP Code Improvement and its Application to Compilers (in Japanese)" Proc.of the 11th Digital Signal Processing Symposium. 693-698 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N.Sugino and A.Nishihara: "Optimization of Memory Addressing for Automatic DSP Code Generation (in Japanese)" Proc.of the 10th Digital Signal Processing Symposium. 325-330 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N.Sugino, S.Yoshida, and A.Nishihara: "An Optimization Method of Memory Addressing for DSP with Multiple Address Registers (in Japanese)" IEICE Technical Report. CAS96-24. 59-66 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N.Sugino, H.Miyazaki, and A.Nishihara: "Optimization of Memory Addressing Utilizing Code without Memory Accesses, and Automatic DSP Code Generation (in Japanese)" IEICE Technical Report. CAS95-19. 51-59 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N.Sugino, H.Miyazaki, and A.Nishihara: "An Improved Memory Address Allocation for DSP Code Optimization (in Japanese)" Proc.of 1996 IEICE Society Meeting, A : Fundamentals. A-105. (1996)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 1999-03-09  

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