| Project/Area Number |
08455178
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
情報通信工学
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| Research Institution | Osaka University |
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Principal Investigator |
SHIRAKAWA Isao Osaka University, Department of Information Systems Engineering, Professor, 工学部, 教授 (10029100)
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| Co-Investigator(Kenkyū-buntansha) |
ONOYE Takao Osaka University, Department of Information Systems Engineering, Research Assist, 工学部, 助手 (60252590)
SHIGEHIRO Yuji Osaka University, Education Center for Information Processing, Research Assistan, 情報処理教育センター, 助手 (40243175)
ISHIURA Nagisa Osaka University, Department of Information Systems Engineering, Associate, Prof, 工学部, 助教授 (60193265)
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| Project Period (FY) |
1996 – 1997
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| Keywords | digital signal processing / VLSI implementation / MPEG / FIR filter |
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| Research Abstract |
In this project, we developed new architectures for video compression and digital filters for video transmission. We also attempted to implement VLSIs based on the architectures.
As for video compression, we developed an architecture for HDTV level MPEG2 encoder/decoder based on dedicated hardware components. We first designed for each process of video encoding/decoding a customized hardware module and then connect them with dedicated networks and memories which are optimally configured. We succeeded in integrating the encoder/decoder facilities on two VLSI chips.
As for digital filters, we developed a novel multiplication algorithm customized for digital filters and implemented a FIR as a VLSI.The algorithm enables very fast with small amount of hardware, making use of the fact that 1) only 8 to 12 bit precision is enough for the digital filters and 2) multiplicand may be a constant coefficient as long as it is programmable. An FIR filter of 11 taps is implemented as a single chip VLSI which operates at 100MHz.
We also made investigation on high-level synthesis system which expediates the design of VLSI.We developed a system which synthesizes from a specification written in C-language an RT-level VHDL description, which can be transformed automatically into layout pattern using existing logic synthesis and layout tools.
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