| Project/Area Number |
08554006
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
素粒子・核・宇宙線
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| Research Institution | High Energy Accelerator Research Organization Institute of Particle and Nuclear Studies |
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Principal Investigator |
MATSUDA Takeshi High Energy Accelerator Research Organization, Institute of Particle and Nucle Studies, Associate Professor, 素粒子原子核研究所, 助教授 (10029564)
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| Co-Investigator(Kenkyū-buntansha) |
SAITOH Yutaka Interchip Corporation, Development Division, Director, 開発部, 部長
HAZUMI Akinori Osaka Uuiversity, Physics Department, Research Assocaite, 大学院・理学研究科, 助手 (20263197)
AIHARA Hiroaki University of Tokyo, Physics Department, Associate Professor, 大学院・理学系研究科, 助教授 (60167773)
FUKUNAGA Chikara Tokyo Metropolitan University, Physics Department, Associate Professor, 大学院・理学研究科, 助教授 (00189961)
IKEDA Hirokazu High Energy Accelerator Research Organization, Institute of Particle and Nucle S, 素粒子原子核研究所, 助教授 (10132680)
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| Project Period (FY) |
1996 – 1998
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| Keywords | Silicon position detector / Pixel detector / pMOS pixel detector / SOI pixel detector / Radiation-hard VLSI / Sub-micron process / Bump bonding |
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| Research Abstract |
The project is to study and develop Silicon pixel detectors based on the PIN diode structure for detection of charged particles and photon. The project also aims at development of basic technologies for the pixel detectors. A pMOS pixel detector prototype was tested successfully for a pion beam at KEK.Three variations of the pMOS device were fabricated and tested to improve the speed of the device, to add a capability to reset each pixel and to improve the response (ovisible photon of shorter wave length. The SOL pixel detector is a new idea to fabricate a pixel detector on the SOI wafer. It should solve the problems of the monolithic pixel device by forming the PIN pixel cells in the high resistive silicon layer of the SOI wafer and fabricating the readout micro electronics on the low resistive SOS layer. Test structures of the SOI pixel device were made to test the contact through the insulator of the SOL wafer between a PIN pixel cell and a readout electronics on the SOS layer. The result showed that some tuning of process parameters were still needed to make the pixel structure and contact, while the readout electronics on the SOS wafer worked as expected. The sub-micron CMOS silicon processes had been speculated to be more radiation-hard because of the thinner oxide-layers. Our test of transistors fabricated by the SII 0.8 micron (low temperature) process showed promising results on the threshold shift of the transistors. We then fabricated a 128ch CMOS preamplifier VLSI, which we have developed in another project, by the 0.8 micron process. The chips are now being prepared for an irradiation test. A solder bump bonding of 50 micron pitch for an actual detector size was also tested successfully at SII.
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