1997 Fiscal Year Final Research Report Summary
Study of all-optical routing system
| Project/Area Number |
08650046
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Applied optics/Quantum optical engineering
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
MIZUMOTO Tetsuya Tokyo Institute of Technology Faculty of Engineering, Associate Professor, 工学部, 助教授 (00174045)
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| Project Period (FY) |
1996 – 1997
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| Keywords | all-optical signal processing / optical switching system / optical nonlinear effect / nonlinear optical loop mirror / address information / time division multiplexing / header bit |
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| Research Abstract |
With the aim of constructing all-optical routing circuits, functional optical circuits, which include a header extraction circuit and an address recognition circuit, are studied. Novel all-optical circuits are proposed. Their operation has been demonstrated successfully at a wavelength of 1550nm.
In the header extraction circuit, a control pulse, which is used for synchronization throughout the proposed circuits, is generated from the transmitted cell attached with start bits. Comparing with conventional schemes, the proposed circuit needs no routing table. The header is separated from the cell without O/E and E/O conversions. The path through which the cell is transmitted is determined by the recognized header information.
In order to demonstrate the operation, the proposed circuit was constructed by using NOLM as all-optical switches. The width and interval of transmitted pulses are 10nsec and 120nsec, respectively, in the header extraction circuit. These are limited only by the facilities available in this experiment. The attainable bit rate is determined only by the response time of optically controlled switch, not by the circuit configuration. Even if we use the NOLM composed of a 2km-long fiber, bit rate of 110Gbps is attainable for input pulse of 4psec FWHM.Optical switches with fast response time, which operate under low control power, are highly desired for a practical application.
The signal that controls switches in the routing network is generated in the proposed address recognition circuit. The operation has been successfully demonstrated for 4bit-address signals in the experiment.
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