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1997 Fiscal Year Final Research Report Summary

Studies on combined arithmetic circuits for high-speed digital signal processing

Research Project

Project/Area Number 08680358
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionNagoya University

Principal Investigator

TAKAGI Naofumi  Nagoya University, Graduate school of Engineering, Associete Professor, 工学研究科, 助教授 (10171422)

Project Period (FY) 1996 – 1997
KeywordsComputer arithmetic / Multiplication / Division / Square rooting / Multiply-addition / Powering / Modular division / Hardware algorithm
Research Abstract

We have developed methods for designing combined arithmetic circuits which execute consecutive addition/subtractions and multiplications appearing in degital signal processing as one operation, and also developed high-speed computing method using these circuits. The main results are as follows :
1. We have designed an add-multiply-adder which executes consecutive addition, multipli-cation and addition appearing often in degital signal processing as one operation, and shown its applications.
2. We have developed a new high-speed square rooting algorithm using a multiply-adder which executes consecutive multiplication and addition as one operation.
3. We have developed a new method for generating powers of an operand, such as recirocal, square root, reciprocal square root, reciprocal square, reciprocal cube and so on, using a multiplier with operand modifier.
4. We have developed an adder which is optimal in theory and very efficient in practice, under the assumption of left-to-righ input arrival.
5. We have developed two hardware algorithms for modular division with very large modulus which is required in cryptosystems. One is based on the extended Euclidean algorithm and the other is based on the binay GCD algorithm.
6. We have developed massively parallel algorithms for executing arithmetic operations on a functional memory and have developed a method for motion vector detection using them.

  • Research Products

    (16 results)

All Other

All Publications (16 results)

  • [Publications] Naofumi Takagi: "A hardware algorithm for modular division based on the extended Euclidean algorithm" IEICE Transactions on Information and Systems. E79-D,11. 1518-1522 (1996)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Naofumi Takagi: "Square rooting by iterative multiply-additions" Information Processing Letters. 60. 267-269 (1997)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Naofumi Takagi: "Efficient intinitial approximation for multiplicative division and square root by a multiplication with operand modification" IEEE Transactions on Computers. 46,4. 495-498 (1997)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Naofumi Takagi: "O(n)-depth modular exponentiation circuit algorithm" IEEE Transactions on Comupters. 46,6. 701-704 (1997)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Naofumi Takagi: "A VLSI algorithm for modular division based on the binary GCD algorithm" IEICE Transactions on Fundamentals of Electronics,Communications and Computer Sciences. E81・A,5(5月発行予定). (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Naofumi Takagi: "Generating a power of an operand by a table look-up and a multiplication" Proceedings of the IEEE 13th Symposium on Computer Arithmetic. 126-131 (1997)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Naofumi Takagi: "A hardware algorithm for modular division based on the extended Euclidean algorithm" IEICE Trans. Info. & Systems. Vol.E79-D,No.11. 1518-1522 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Naofumi Takagi: "Square Rooting by Iterative Multiply-Additions" Information Processing Letters. no.60. 267-269 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Naofumi Takagi: "Efficient Initial Approximation for Multiplicative Division and Square Root by a Multiplication with Operand Modification" IEEE Trans. Computers. Vol.46, No.4. 495-498 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Naofumi Takagi: "O (n) -Depth Modular Exponentiation Circuit Algorithm" IEEE Trans. Computers. Vol.46, No.6. 701-704 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Naofumi Takagi: "A VLSI Algorithm for Modular Division Based on the Binary GCD Algorithm" IEICE Trans. Fundamentals. Vol.E81-A,no.5 (to appear). (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Naofumi Takagi: "Generating a Power of an Operand by a Tabie Look-up and a Multiplication" Proc.13th IEEE Symp. Computer Arithmetic. 126-131 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Naofumi Takagi: "A motion vector detection algorithm for moving video compression using functional memory" IEICE Technical Report. COMP96-56. (1996)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Naofumi Takagi: "Efficient adder under left-to-right input arrival" IEICE Technical Report. COMP97-21. (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Naofumi Takagi: "Generation of reciprocal, square root, and so forth by means of a multiplier with an operand modifier" IEICE Technical Report. COMD5P97-112. (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Naofumi Takagi: "A redundant basis for fast iterative multiplication on GF (2^m) and a parallel multiplier based on it." IEICE Technical Report. COMP97-83. (1998)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 1999-03-16  

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