| Project/Area Number |
09044196
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| Research Category |
Grant-in-Aid for international Scientific Research
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| Allocation Type | Single-year Grants |
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| Section | Joint Research |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Fuzzy Logic Systems Institute |
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Principal Investigator |
YAMAKAWA Takeshi Fuzzy Logic Systems Institute, Chairman, 理事長 (00005547)
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| Co-Investigator(Kenkyū-buntansha) |
SANCHEZ Elie Univ.of Marseille, Prof., 教授
ZURADA Jacek Univ.of Louisiville, Prof., 教授
SZU Harold Naval Surface Warfare Center, Senior Scientist, 主任研究員
MIKI Tsutomu Fuzzy Logic Systems Institute, Staff Scientist, 研究員 (20231607)
UCHINO Eiji Fuzzy Logic Systems Institute, Senior Scientist, 主任研究員 (30168710)
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| Project Period (FY) |
1997 – 1998
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| Keywords | chaos unit / saturated N-shaped nonlinear function / saturated inverse-N shaped nonlinear function / chaotic itinerancy / non-equilibrium cross-coupled network / chaos memory / global minimum / Traveling Salesman Problem (TSP) |
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| Research Abstract |
The possibility of an associative memory, which is constructed by cross-coupling the chaos units, is discussed considering silicon implementation. The following conclusions are obtained from this research.
1. Design of a Chaos Unit : The chaos unit is constructed with a nonlinear device and a delay element.
(1) It is a saturated inverse-N-shaped nonlinear function that is suitable for realizing effective chaotic itinerancy.
(2) It is a saturated N-shaped nonlinear function that is suitable for solving Traveling Salesman Problem. The network employing this nonlinear devices guarantees the global minimum in obtaining the solution by increasing the gains of weighting factors.
(3) The internal value of each chaos unit, the weighted sum of inputs, can be the detectable measure of similarity to design the network.
2. Suitability for Silicon Implementation
(1) The chaos unit of interest exhibits simplicity and thus is suitable for an integrated circuit.
(2) The chaos network obtained in this research is insensitive to the variance of device dimensions to be stable in dynamical behavior and thus is suitable for an integrated circuit.
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