1999 Fiscal Year Final Research Report Summary
Study on Singl-Transistor-Cell-Type Ferroelectric Memory
| Project/Area Number |
09305025
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
ISHIWARA Hiroshi Tokyo Institute of Technology, Frontier Collaborative Research Center, PROFESSOR, フロンティア創造共同研究センター, 教授 (60016657)
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| Co-Investigator(Kenkyū-buntansha) |
YAMAMOTO Shuu'itiro Tokyo Institute of Technology, Frontier Collaborative Research Center, ASSISTANT, フロンティア創造共同研究センター, 助手 (50313375)
AIZAWA Koji Tokyo Institute of Technology, Precision and Intelligence Lab., ASSISTANT, 精密工学研究所, 助手 (40222450)
TOKUMITSU Elisuke Tokyo Institute of Technology, Precision and Intelligence Lab., RESEARCH ASSOCIATE, 精密工学研究所, 助教授 (10197882)
OHMI Shun-ichiro Tokyo Institute of Technology, Precision and Intelligence Lab., ASSISTANT, 精密工学研究所, 助手 (30282859)
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| Project Period (FY) |
1997 – 1999
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| Keywords | Ferroelectric / Memory / SOI / Silicon / YMnO_3 / SrBi_2Ta_2O_9 |
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| Research Abstract |
In this year, it was first pointed out that a simple MFSFET (metal-ferroelectric-semiconductor field effect transistor) structure was not suitable to keep a long retention time of the memory. Thus, it was recommended to insert a buffer layer between the ferroelectric film and Si substrate. As a candidate of the buffer layer, Y_2O_3 was used and PLZT ( (Pb, La)(Zr, Ti) O_3) was formed on it. The reasons why we chose PLZT are as follows : (1) PLZT can be formed at relatively low temperature so that the Y_2O_3 buffer does not degrade during the thermal process to fcrm PLZT, and (2) the remnant polarization of PLZT is lower than that of PZT.As a result, good C-V characteristic of Pt/PLZT/Pt/Y_2O_3/Si diodes were obtained when the area of the MFM part composed of Pt/PLZT/Pt structure was reducted to 1/15 of the area of the MIS (Pt/ Y_2O_3/Si) part.
Next, a doucble-layer of SrTa_2O_6 and SiON was used as the buffer layer to deposit SBT (SrBi_2Ta_2O_9). where SiON was used to prevent the oxidation of Si surface. The device structure of MFMIS-FET's was so designed that the operation voltage became low. Under the optimum conditions where the area ratio largr than 10 was adopted, the current on-off ratio larger than 10^3 was retained for more than 10 hours at low operation voltage of 3.5V.It is concluded from these results that the optimization of the area ratio is most important in obtaining good retention characteristic.
Finally, formation of SBT films was conducted using liquid-deliver MOCVD method, in which Bi(C_6H_5)_3 and Sr[Ta(OC_2H_5)_6]_2 were used. It was found that nearly stoichiometric films were formed at lower temperature than 400℃, and ferroelectricity was observed.
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