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1999 Fiscal Year Final Research Report Summary

Constitution of Neuro-based Dynamic Memory

Research Project

Project/Area Number 09450135
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field 電子デバイス・機器工学
Research InstitutionTohoku University

Principal Investigator

NAKAJIMA Koji  Research Institute of Electrical Communication, Tohoku University, Professor, 電気通信研究所, 教授 (60125622)

Co-Investigator(Kenkyū-buntansha) ONOMI Takeshi  Research Institute of Electrical Communication, Tohoku University, Research Associate, 電気通信研究所, 助手 (70312676)
SATO Shigeo  Research Institute of Electrical Communication, Tohoku University, Research Associate, 電気通信研究所, 助手 (10282013)
Project Period (FY) 1997 – 1999
KeywordsNeural Network / Dynamic Memory / Neuro Chip / Integrated Circuit / Chaos / Limit Cycle / Non-monotonic Neuron / Associative Memory
Research Abstract

The purposes of this research are analyses for behaviors of neuro-based dynamic memories, research for applications of the memories, a constitution of the memory, analyses for learning ability of the memories, a hardware integration of the memories aimed at real time processings. We analyzed the number of limit cycles generated in a single neural network by using a proposed learning algorithm. We also analyzed the characteristics of the limit cycles and transition states to the limit cycles, and characteristics of a non-monotonic neuron network which has a higher performance of learning ability. Interactions among the limit cycles, initial states, and chaotic noise were investigated on fabricated neuro-chips with integrated chaotic signal generators. In order to investigate dynamic behaviors of quantized interconnection networks on neuro-chips, we have designed and fabricated a hardware neural network according to the design rule of a CMOS technology. The 225 (and 42) full connections between 15 (and 7) neurons and the self-couplings can be performed in the fabricated neuro-chip. The number of limit cycles which can be produced on the single network increases sharply with increasing the number of neurons in case of nearest neighbor connections. For an example, 1.14x10ィイD17ィエD1 limit cycles in the case of 40 neurons are estimated at least. The limit cycles have basins of attraction, and hence, we may utilize the network as associative memeory to retrieve dynamical cyclic patterns. We also presented the quantized interconnection network to solve the N-parity problem and a random Boolean function with arbitrary N inputs. Finally, we discussed the learning possibility for the quantized interconnection networks. These results show the high performance of the neuro-based dynamic memories and the high possibility of applications of the memory as intelligent information processors.

  • Research Products

    (23 results)

All Other

All Publications (23 results)

  • [Publications] Tomochika Harada et al.: "New Nonvolatile Analog Memories for Building Associative Memories"Ext.Abst.of the 1999 Int.Conf.on Solid-State Devices and Materials. 270-271 (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Cheol-Young Park et al.: "Analog CMOS Implementation of Quaritized Interconnection Neural Networks for Memorizing Limit Cycles"IEICE Trans.on Fundamentals. E82-A. 952-957 (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Hidetoshi Tanaka et al.: "Integrated Circuits of Map Chaos Generators"IEICE Trans.on Fundamentals. E82-A. 364-369 (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Tomochika Harada et al.: "A Content-Addressable Memory Using"Switched Diffusion Analog Memory with Feedback Circuit""IEICE Trans.on Fundamentals. E82-A. 370-377 (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Tomochika Harada et al.: "A New Floating-Gate Analog Memory and An Analog Content-Adressable Memory for Building A New Intelligent System"Proc.of the Workshop on Synthesis And System Integration of Mixed Technologies. 256-263 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Koji Nakajima: "Dynamic Behaviors of an integrated circuit for recurrent neural networks"Proc.of 1998 Second Int.Conf.on knowledge-Based Intelligent Electronic Systems. 3. 260-267 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] H. Tanaka, S. Sato, and K. Nakajima: "Integrated Circuits of map Chaos Generators"IEICE Trans. Fundamentals. E82-A, 2. 364-369 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Harada, S. Sato, and K. Nakajima: "A Content-Addressable Memory Using Switched Diffusion Analog Memory with Feedback Circuit"IEICE Trans. Fundamentals. E82-A, 2. 370-377 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] C. Park and K. Nakajima: "Analog CMOS Implementation of Quantized Interconnection Neural Networks for Memorizing Limit Cycles"IEICE Trans. Fundamentals. E82-A, 6. 952-957 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Harada, Y. Mizugaki, and K. Nakajima: "A new analog content addressable memory for building a new intelligent system and VLSI implementation"Proceedings of 1997 Int. Symposium on Nonlinear Theory and its Applications. Vol. 2. 869-872 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] H. Tanaka, S. Sato, K. Nakajima, E. Belhaire, and P. Garda: "Designs of integrated circuit to generate map chaos"Proceedings of 1997 Int. Symposium on Nonlinear Theory and its Applications. Vol. 2. 873-876 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] S. Sato, S. Shibata, and K. Nakajima: "A study on the learning ability of a DBM with quantized synapses"Proceedings of 1997 Int. Symposium on Nonlinear Theory and its Applications. Vol. 2. 887-880 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K. Nakajima: "Integrated circuit of quantized interconnection networks"Proceedings of the second R.I.E.C. Int. Symposium. 118-123 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Yamada, K. Nakajima, Y. Hayakawa, and Y. Sawada: "Application of chain neural network with a cyclic connection for taking in external cyclic pattern"Proceedings of the second R.I.E.C. Int. Symposium. 201-204 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] H. Tanaka, S. Sato, K. Nakajima, E. Belhaire, and P. Garda: "Simple integrated circuits for a chaotic noise generator"Proceedings of the second R.I.E.C. Int. Symposium. 279-282 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Harada, Y. Mizugaki, and K. Nakajima: "A new analog content addressable memory for building a new intelligent system and VLSI implementation"Proceedings of the second R.I.E.C. Int. Symposium. 283-286 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] M. Kinjo, S. sato, and K. Nakajima: "On high learning ability of DBM with non-monotonic neurons"Proceedings of the second R.I.E.C. Int. Symposium. 287-290 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K. Nakajima: "Dynamic behaviors of an integrated circuit for recurrent neural networks"Proceedings of 1998 second Int. Conf. On Knowledge-Based Intelligent Electronic Systems. vol. 3. 260-267 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K. Nakajima: "Layered Neural Networks with Quantized Interconnections"Proceedings 1998 Int. Symposium on Nonlinear Theory and its Applications. vol. 2. 459-462 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] M. Kinjo, S. Sato, and K. Nakajima: "DBM learning in non-monotonic neural networks"Proceedings 1998 Int. Symposium on Nonlinear Theory and its Applications. vol. 2. 455-458 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] C. Park, Y. Katayama, and K. Nakajima: "Implementation of quantized connection neural networks and its application for pattern classifier"Proceedings of ITC-CSCC'98. 1077-1080 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K. Nakajima and S. Sato: "Hardware integration for neural networks in RIEC Tohoku University"Proceedings of ICCCS'98 (The 1998 International Conference on Computers, Communications and Systems). 5-14 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Harada, S. Sato, and K. Nakajima: "A New Floating-Gate Analog Memory and an Analog Content-Addressable Memory for Building a New Intelligent system"Proceedings of the Workshop on Synthesis And System Integration of Mixed Technologies. SASIMI'98. 256-263 (1998)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 2001-10-23  

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