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1999 Fiscal Year Final Research Report Summary

super-high access-bandwidth common-memory architecture for elector-optical integration

Research Project

Project/Area Number 09450144
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field 電子デバイス・機器工学
Research InstitutionHiroshima University

Principal Investigator

MATTAUSCH Hans J.  Res. Center for Nanodev. and Systems, Hiroshima University, Professor, ナノデバイス・システム研究センター, 教授 (20291487)

Co-Investigator(Kenkyū-buntansha) NAGATA Makoto  Faculty of Engineering, Hiroshima University, Research Associate, 工学部, 助手 (40274138)
IWATA Atsushi  Faculty of Engineering, Hiroshima University, Professor, 工学部, 教授 (30263734)
YOKOYAMA Shin  Res. Center for Nanodev. and Systems, Hiroshima University, Professor, ナノデバイス・システム研究センター, 教授 (80144880)
Project Period (FY) 1997 – 1999
KeywordsCommon Memory / Multiport Memory / Copy Bus / Access Conflict / Hierarch. Architecture / Electro-optical Integration
Research Abstract

The purpose of this research project was to find a new high-bandwidth common memory architecture, which substantially advances the state of the art in this field, so that high-bandwidth common memories become applicable in practice. A special question was, whether electro-optical integration, with signal transmission by light over optical wave-guides, is necessary for achieving this aim.
The main result of the project is the development and verification of a new area-efficient hierarchical multiport-memory architecture. This architecture enables genuine common memories with large storage capacities and terabit-per-second access bandwidth in practice. Terabit-per-second access bandwidth becomes possible by the implementation of ,up to 32 ports with independent and parallel access capability. Both area-efficiency and access-bandwidth can be improved by an order of magnitude in comparison to the previous state of the art. The access-bandwidth increases approximately proportional to the port-number. The area-reduction factors have been investigated quantitatively for the case of the SRAM. They amount to <1/2, <1/5, <1/14 and <1/30 for the cases of 4, 8, 16 and 32 ports, respectively.
Electro-optical integration is not necessary for achieving this technological breakthrough. For even higher bandwidth and more than 32 ports, we have developed a new copybus common-memory architecture, which then is expected to need signal transmission by light over optical wave-guides for realizing the necessary high throughput of the copybusses.

  • Research Products

    (12 results)

All Other

All Publications (12 results)

  • [Publications] Mattausch,Hans Jurgen: "Hierarchical architecture for area-efficient integrated N-port memories with latencyfree multu-gigabit per second access bandwidth"IEE Electronics Letters. 35. 1441-1443 (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 籠見 嘉之: "Fast quadratic increase of multiport-storage-cell area with port number"IEE Electronics Letters. 35. 2185-2187 (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Mattausch,Hans Jurgen: "Aera-Efficient Multiport Memories for the This Tb/s Bandwidth Era"Proceed.25th European Solid-State Circuits Conference. 126-129 (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Mattausch,Hans Jurgen: "Application of Port-Access-Rejection Probability Theory for lntegrated N-Port Memory Architecture Optimization"IEE Electronics Letters. 34. 861-862 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 山田 耕太郎: "An Area-Efficient Circuit Concept for Dynamical Conflict Management of N-Port Memories with Multi-GBit/s Access Bandwidth"Proceed.24th European Solid-State Circuits Conference. 140-143 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Mattausch,Hans Jurgen: "Hierarchical N-Port Memory Architecture Based on 1 -Port Memory Cells"Proceed.23rd European Solid-State Circuits Conference. 348-351 (1997)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] H.J. Mattausch: "Hierarchical architecture for area-efficient integrated N-port memories with latency-free multi-gigabit per second access bandwidth"IEE Electronics Letters. 35. 1441-1443 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Y. Tatsumi: "Fast quadratic increase of multiport-storage-cell area with port number"IEE Electronics Letters. 35. 2185-2187 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] H.J. Mattausch: "Aera-Efficient Multiport Memories for the Tb/s Bandwidth Era"Proceed. 25th European Solid-State Circuits Conference. 126-129 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] H.J. Mattausch: "Application of Port-Access-Rejection Probability Theory for Integrated N-Port Memory Architecture Optimization"IEE Electronics Letters. 34. 861-862 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K. Yamada: "An Area-Efficient Circuit Concept for Dynamical Conflict Management of N-Port Memories with Multi-Gbit/s Access Bandwidth"Proceed. 24th European Solid-State Circuits Conference. 140-143 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] H.J. Mattausch: "Hierarchical N-Port Memory Architecture Based on 1-Port Memory Cells"Proceed. 23th European Solid-State Circuits Conference. 348-351 (1997)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 2001-10-23   Modified: 2021-04-07  

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