1999 Fiscal Year Final Research Report Summary
Studies on Metal/Ferroelectric/Insulator/Semiconductor (MFIS) -FET Memories Obeying The Scaling Rule
| Project/Area Number |
09450147
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Waseda University |
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Principal Investigator |
SHOJI Shuichi Waseda University, School of Science and Engineering, Professor, 理工学部, 教授 (00171017)
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| Project Period (FY) |
1997 – 1999
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| Keywords | Ferroelectric materials / Memory / MFIS-FET / Scaling / CeOィイD22ィエD2 / Self-align process / High Aspect ratio / 3 layers resist method |
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| Research Abstract |
Metal/Ferroelectric/Insulator/Semiconductor (MFIS)-FET memories have been studied. MFIS-FET memory in which the surface potential of Si is controlled by the remanent polarization of ferroelectric materials, has the significant advantages of obeying the scaling rule, high switching speed, nonvolatility, radiation tolerance and high density. The results of our work are as follows.
(1) Fabrication of the Metal/Ferroelectric/Insulator/Semiconductor (MFIS) structures
To obtain a good interface which acts as the gate oxide for Metal/Ferroelectric/Semiconductor (MFS)-FETs and to obtain ferroelectric films with preferred for use as intermediate layers between the ferroelectric material and the Si sybstrate for MFIS-FETs. By using ceria-zirconia mixture (Ce・ZrOィイD22ィエD2) films on Si substrate, CeOィイD22ィエD2 can be grown epitaxially. Ce-Ce・ZrOィイD22ィエD2 films are good intermediate layers between a ferroelectric material and Si (100) for MFIS-FET. We also developed a deposition method of PLZT on CeOィ
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イD22ィエD2 buffer layer using the sol-gel method. By optimizing the annealing steps, PLZT can be also grown hetero epitaxially. On the other hand, MSIF structure having the SrBiィイD22ィエD2TaィイD22ィエD2OィイD29ィエD2 (SBT) as a poly crystalline ferroelectric material are also fabricated using SiON as a intermediate layer, which shows good C-V characteristics.
(2) Fabrication of the MFIS-FET with self-alignment technique
To obtain microfabrication of MFIS-FETs with good high frequency characteristics, self-alignment technique was developed. A Pt, SBT and SiON were used as the gate metal, the ferroelectric material and the buffer layer. These three layers are patterned by the plasma dry etching with a single photoresist mask. The W/L of the MSIF-FET was 700/150 μm. To reduce the gate dimensions, reactive ion etching (RIE) is requested for the etching.
(3) Studies on microfabrication methods of MFIS-FETs
In order to fabricate 1μm or smaller than 1 μm gate MFIS-FETs with simple self-alignment process, a high aspect ratio mask layer is needed. UV photoresist of EPON SU-8 was utilized for this purpose. Fine resolution of 1.5 μm with aspect ratio of 8 was obtained. We also studied three layer resist method using EB direct writing and RIE method. High resolution of about 0.5μm with aspect ratio of about 6.5 was realized. Less
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