1999 Fiscal Year Final Research Report Summary
Theory and design of fault tolerant integrated systems
| Project/Area Number |
09450158
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
System engineering
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| Research Institution | Japan Advanced Institute of Science and Technology |
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Principal Investigator |
KANEKO Mineo JAIST, School of Information Science, Associate Professor, 情報科学研究科, 助教授 (00185935)
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| Co-Investigator(Kenkyū-buntansha) |
TAYU Satoshi JAIST, School of Information Science, Research Associate, 情報科学研究科, 助手 (20293392)
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| Project Period (FY) |
1997 – 1999
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| Keywords | fault tolerance / reconfiguration / error correction / multi-processor / parallel computation / systolic array / fault detection / diagnosis / multiplication |
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| Research Abstract |
The aim of this research project is to establish bases for fault tolerant integrated systems which have the potential to correct errors concurrently and to reconfigure themselves so as to exclude faulty components. The major contributions of this project are summarized in the following.
1. On-line fault detection and diagnosis for parallel computing systems : We have proposed graph-theoretic model for analysis and synthesis of algorithm-based fault-tolerance systems. Based on this model, we have developed several checking schemes and operation / checking mapping schemes for single-fault-locatable/double-fault-detectable systems.
2. On-line error correctable parallel computing on systolic arrays : Fault tolerant systolic array based on Triple Modular Redundancy in mixed spatial-temporal space has been proposed. In this scheme, not only computations but also communications are multiplicated, and link sharing is necessary to reduce its link complexity. Link sharing scheme which guarantees high reliability and schedulability has been also proposed.
3. Reconfiguration for fault tolerant network computing on WSIs : Reconfiguration algorithm for torus networks has been proposed. Necessary and sufficient hardware(interconnection resource) redundancy required for this reconfiguration algorithm has been also investigated.
Extension to control-intensive applications and a fusion of on-line correctability and reconfigurability are problems to be tackled in future.
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