2000 Fiscal Year Final Research Report Summary
BASIC STUDIES ON VLSISYNTHESIS FOR TESTABILITY FROM HIGHER LEVEL
| Project/Area Number |
09480054
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| Research Category |
Grant-in-Aid for Scientific Research (B).
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | NARA INSTITUTE OF SCIENCE AND TECHNOLOGY |
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Principal Investigator |
FUJIWARA Hideo NARA INSTITUTE OF SCIENCE AND TECHNOLOGY, GRAD.SCHOOL OF INFORMATION SCIENCE, PROFESSOR, 情報科学研究科, 教授 (70029346)
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| Co-Investigator(Kenkyū-buntansha) |
井上 美智子 奈良先端科学技術大学院大学, 情報科学研究科, 助教授 (30273840)
INOUE Tomoo HIROSHIMA CITY UNIVERSITY, GRAD.SCHOOL OF INFORMATION SCIENCES, ASSOCIATE PROFESSOR, 情報科学部, 助教授 (40252829)
MASUZAWA Toshimitsu OSAKA UNIVERSITY, GRAD.SCHOOL OF ENGINEERING SCIENCE, PROFESSOR, 大学院・基礎工学研究科, 教授 (50199692)
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| Project Period (FY) |
1997 – 2000
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| Keywords | DESIGN FOR TESTABILITY / SYNTHESIS FOR TESTABILITY / HIGHLEVEL SYNTHESIS / VLSITEST / DATA FLOW GRAPH / REGISTER TRANSFERLEVEL / DATA PATH / CONTROLLER |
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| Research Abstract |
Consideration to testability from the early stage in the design process is one of the most effective ways to reduce testing cost. In this study, we proposed several approaches to high-level test synthesis and register-transfer level (RTL) design, especially for targeting non-scan design. We presented high-level synthesis methods that consider testability of generated RTL data paths, as well as their area and performance. We also presented several non-scan design-for-testability (DFT) methods at RTL to achieve complete (100%) fault efficiency. Our experimental results using benchmarks and real designs showed the effectiveness of our proposed methods. The research results are as follows :
(1) A HIGH-LEVEL SYNTHESIS METHOD FOR WEAKLY TESTABLE DATA PATHS
(2) A NON-SCAN DFT METHOD FOR DATA PATHS TO ACHIEVE COMPLETE FULT EFFICIENCY
(3) A NON-SCAN DFT METHOD FOR CONTROLERS TO ACHIEVE COMPLETE FULT EFFICIENCY
(4) A NON-SCAN DFT METHOD AT REGISTER-TRANSFER LEVEL TO ACHIEVE COMPLETE FAULT EFFICIENCY
(5) A PARTIAL SCAN DESIGN FOR TESTABILTY METHOD BASED ON ACYCLIC STRUCTURE
(6) A HIGH-LEVEL SYNTHESIS APPROACH TO PARTIAL SCAN DESIGN BASED ON ACYCLIC STRUCTURE
(7) AN APPROACH TO BIST FOR RTL DATA PATHS BASED ON SINGLE-CONTROL TESTABILITY
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