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1998 Fiscal Year Final Research Report Summary

Rapid Prototyping Technology for Large Scale Logic Circuits

Research Project

Project/Area Number 09559014
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section展開研究
Research Field 広領域
Research InstitutionKumamoto University

Principal Investigator

SUEYOSHI Toshinori  Kumamoto University, Faculty of Engineering, Professor, 工学部, 教授 (00117136)

Co-Investigator(Kenkyū-buntansha) SHIROUZU Hiroshi  Kyushu Matsushita Electric Co., LTD., Researcher, 技術本部テレコム研究所, 研究員
SHIBAMURA Hidetomo  Kumamoto University, Faculty of Engineering, Research Associate, 工学部, 助手 (10264136)
SASAKI Mamoru  Kumamoto University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (70235274)
KUGA Morihiro  Kumamoto University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (80243989)
Project Period (FY) 1997 – 1998
KeywordsPapid Prototyping / EPGA / Logic Partitioning / Hardware Description Language / Large Scale Logic Circuit / System LSI
Research Abstract

As mentioned in the research plan, we study Rapid Prototyping Technology for Large Scale Logic Circuits. The followings are major results of the research.
1. We developed interactive logic partitioning method which divides gate level netlist into FPGAs utilizing knowledge of designer. This method enables effective logic partitioning independent of design entries such as schematic capture and hardware description language. Utilization ratio and operation speed of FPGA are improved.
2. In addition to method I., two automatic logic partitioning methods were introduced into rapid prototyping environment, which divide logic circuits from gate level netlist and hardware description language. Combining three partitioning methods provided more efficient prototyping environment.
3. We applied the rapid prototyping environment to VLSI system design education. Adopting Graphical HDL entry tool, design specifications of developing system were immediately utilized design entry. It provided not only effective design methods but also design tool for novice designers.
4. We applied the rapid prototyping environment to image processing LSI design for multimedia equipment. This results show that it provided easily to investigation a suitable architecture for operation speed and circuit size using LPGA.

  • Research Products

    (12 results)

All Other

All Publications (12 results)

  • [Publications] 児玉,宣貴: "LPGAによるリアルタイム動画像圧縮符号化用動き検出LSIの開発" Proc.5th FPGA/PLD Conference & Exhibit予稿集. 279-288 (1997)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 佐々木,守: "最適値探索を行うHopfieldモデルのパラメータのバラツキに対する低感度化" 電子情報通信学会誌. J80-A巻6号. 926-935 (1997)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 奥村,勝: "並列離散事象シュミレーション評価環境VPSEとタイムワープ手法の性質検討" 情報処理学会論文誌. 39巻6号. 1571-1580 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 末吉,敏則: "リコンフィギャラブルロジック" 電子情報通信学会誌. 81巻11号. 1100-1106 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 末吉,敏則: "FPGAの現状と将来動向" 第2回システムLSI琵琶湖ワークショップ予稿集. 93-101 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 佐々木,守: "2値化画像処理機能を集積化したアナログVLSIの構成" 電子情報通信学会論文誌. (採録決定). (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Nobutaka Kodama: "Design and Implementation of Motion Estimation for real time video image compression using LPGA" Proceedings of the 5th Japanese FPGA/PLD Conference & Exhibit. 279-288 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Mamoru Sasaki: "Realization of Low Sensitivity on Hopfield Model for Optimal-Solution Search" The Transactions of the Institute of Electronics, information and Communication Engineers. Vol.J80-A,No.6. 926-935 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Masaru Okumura: "VPSE : An Evaluation Environment for Parallel Discrete-Event Simulation and Its Case Study on Time Warp" Transactions of Information Processing Society of Japan. Vol.39, No.6. 1571-1580 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Toshinori Sueyoshi: "Reconfigurable Logic" The Journal of the Institute of the Electronics, Information and Communication Engineers. Vol.18, No.11. 1100-1106 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Toshinori Sueyoshi: "Present and Future Trends of Field Programmable Gate Arrays" Proceedings of the 2nd Biwako Workshop on System LSI. 93-101 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Mamoru Sasaki: "An Analog VLSI for Analog-to-Binary Image Conversion" The Transactions of the Institute of the Electronics, Information and Communication Engineers. (to appear). (1999)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 1999-12-08  

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