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1998 Fiscal Year Final Research Report Summary

Optimization of detailed design for UDSM (ultra deep submicron) integrated circuits

Research Project

Project/Area Number 09650383
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field 電子デバイス・機器工学
Research InstitutionKYOTO UNIVERSITY

Principal Investigator

ONODERA Hidetoshi  Kyoto University, Dept.of Communications and Computer Engineering, Associate Professor, 情報学研究科, 助教授 (80160927)

Co-Investigator(Kenkyū-buntansha) KOBAYASHI Kazutoshi  Kyoto University, Dept.of Communications and Computer Engineering, Research Asso, 情報学研究科, 助手 (70252476)
TAMARU Keikichi  Kyoto University, Dept.of Communications and Computer Engineering, Professor, 情報学研究科, 教授 (10127102)
Project Period (FY) 1997 – 1998
Keywordsoptimization of detailed design / Low power design / High speed design / Cell-base design / Library generation / Standard cell library / Gate sizing / Input reordering
Research Abstract

We have studied design optimization methods for UDSM integrated circuits. In particular, we have developed a gate-level optimization method combined with layout design(we call this "detailed design") and its related techniques.
In the detailed design, accurate delay and power estimation are necessary. We have developed an quasi-analytical method for delay and power estimation of CMOS gates driving a CRC pi load. The error of the estimated delay is around 3% in average while the calculation speed is 1000 times faster than circuit simulation.
The target of the detailed design optimization is a cell-base designed ASIC.In this case, the performance of the cell library directly affects the performance of the designed ASIC.We have developed a generation system of a standard cell library with optimized performance for a target design.
As for the methods for detailed design optimization, we have worked on input reordering and gate sizing. Power dissipation, as well as delay, is optimized by these methods. We have focused on the power dissipated by glitches. Considering glitch reduction in the optimization process, we have succeeded to reduce power dissipation further from the minimum sized circuit that has the lowest capacitive load.

  • Research Products

    (12 results)

All Other

All Publications (12 results)

  • [Publications] M.Hashimoto: "A Power Optimization Method Considering Glitch Reduction by Gate Sizing" Proc.1998 IEEE/ACM ISLPED. 221-226 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] A.Hirata: "Estimation of Propagation Delay Considering Short-Circuit Current for Static CMOS Gates" IEEE Trans. Circuits and Systems II. Vol.45, No.11. 1194-1198 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] M.Hashimoto: "A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits" IEICE Trans. Fundamentals. E82-A, No.1. 159-166 (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 小野寺秀俊: "P2Lib : スタンダードセルライブラリ自動生成システム" 情報処理学会論文誌掲載決定. Vol.40, No.4. (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 平田昭夫: "抵抗分を含む負荷を駆動するCMOS論理回路のゲート遅延時間計算手法" 情報処理学会論文誌掲載決定. Vol.40, No.4. (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 橋本昌宜: "グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法" 情報処理学会論文誌掲載決定. Vol.40, No.4. (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] M.Hashimoto, H.Onodera, and K.Tamaru: "A Power Optimization Method Considering Glitch Reduction by Gate Sizing, "" Proc.IEEE/ACM 1998 ISLPED. 221-226 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] A.Hirata, H.Onodera, and K.Tamaru: "Estimation of Propagation Delay Considering Short-Circuit Current for Static CMOS Gates, "" IEEE Trans.Circuits and Systems-I. Vol.45. 1194-1198 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] M.Hashimoto, H.Onodera, and K.Tamaru: "A Power and Delay Optimization Method Using Input Reorderingin Cell-Based CMOS Circuits, "" IEICE Trans.Fundamentals. Vol.E82-A. 159-166 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] H.Onodera, A.Hirata, T.Kitamura, K.Kobayashi, and K.Tamaru: "P2Lib : Process Portable Library and Its Generation System, "" Trans.IPSJ.Vol.40(to appear). (1999)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] A.Hirata, T.Kondo, H.Onodera, and K.Tamaru: "A Timing Model for CMOS Logic Gates Driving a Capacitive-Resistive Load, "" Trans.IPSJ. Vol.40(to appear ). (1999)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] M.Hashimoto, H.Onodera, and K.Tamar: "A Power Optimization Method Considering Glitch Reduction by Gate Sizing, "" Trans.IPSJ. Vol.40(to appear). (1999)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 1999-12-08  

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