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1998 Fiscal Year Final Research Report Summary

Memory Access Utilizing Indirect Memory Addressing Operations

Research Project

Project/Area Number 09650401
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field 情報通信工学
Research InstitutionTOKYO INSTITUTE OF TECHNOLOGY

Principal Investigator

NISHIHARA Akinori  Tokyo Institute of Technology, Center for Research and Development of Educational Technology, Professor, 教育工学開発センター, 教授 (90114884)

Co-Investigator(Kenkyū-buntansha) SUGINO Nobuhiko  Tokyo Institute of Technology, Graduate School of Science and Engineering, Lectu, 総合理工学研究科, 講師 (60242286)
Project Period (FY) 1997 – 1998
KeywordsMemory Access / Indirect Memory Addressing / Access Graph / Address Allocation / Code Optimization
Research Abstract

In order to achieve high computational performance for recent applications, not only effective use of hardware resources such as arithmetic units and registers, but also efficient access of large memory space is very important. In many of addressing modes, we have indirect addressing mode, which points an access address by the dedicated register called "Address Register (AR)". Usually, simple AR update operations such as AR*1 are allowed to execute together with arithmetic operations in one instruction cycle. Such indirect addressing can be easily implemented at very low hardware cost, and has much advantage to realize a certain memory access such as sequencial array access and so on. Suppose we use this indirect addressing for all the memory access of a given program written in a general purpose language, object code generated by available compiler techniques often includes huge number of overhead concerned with memory access. In this research project, a processor only of indirect mem … More ory addressing mode is assumed, various code optimization methods to reduce memory access overhead are discussed. In the previous method, indirect addressing with AR*1 operations is assumed. The method represents a given memory access by a graph notation or an access graph (AG in short), and then, based on the line graph extraction algorithm, determines an efficient memory allocation of variables in a given program together with an efficient AR assignment for every memory access. In this project, extended indirect addressing models with additional AR operations are assumed, and new heuristic algorithms for code optimization are investigated.
At first, an indirect addressing with additional AR *2 update operations is introduced. Since a triangle shaped graph and its chain structure (Chained Triangle Graph CTG) give efficient memory address allocations, the memory allocation method based on the CTG extraction from an AG is proposed. This method is extended for indirect addressing with AR*1, AR*2, ..., AR*k update operations. The method is based on the Chained Clique Graph (CCG) extraction from an AG.The proposed methods are applied to the compiler, and efficient address allocations are derived for several examples.
Second, modulo AR update operations, such as AR*1MOD4, are newly considered in indirect addressing. A class of AG suitable for this new addressing model is shown, and a memory allocation method based on extraction of this specific shaped graph (Chained Square Graph CSG) is proposed. From address allocation examples, the method is proved to be effective.
All the methods presented above just require a memory access sequence, i.e. a sequence of variables in a given program, so that they are applicable for various compilers. Less

  • Research Products

    (15 results)

All Other

All Publications (15 results)

  • [Publications] N.Sugino, S.Miyazaki, and A.Nishihara: "DSP Code Optimization Methods utilizing Addressing Operations at the Codes without Memory Accesses" IEICE Trans. Fundamentals. E80-A,12. 2562-2571 (1997)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] N.Sugino and A.Nishihara: "Memory Allocation Methods for a DSP with Indirect Addressing Modes and their Application to Compilers" Proceedings 1996 International Symposium on Circuits and Systems. 2585-2588 (1997)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] N.Kogure, N.Sugino, and A. Nishihara: "Memory Allocation Method for Indirect Addressing DSPs with ±2 Update Operations" IEICE Trans. Fundamentals. E81-A, 3. 420-428 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 木暮 央, 杉野 暢彦, 西原 明法: "アドレスレジスタの±2以内の更新命令によるアドレス配置の最適化手法" 第10回回路とシステム軽井沢ワークショップ論文集. 403-408 (1997)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 木暮 央, 杉野 暢彦, 西原 明法: "更新レンジの広い複数アドレスレジスタによる間接アドレッシングDSPのメモリアドレス配置手法" 第11回回路とシステム軽井沢ワークショップ論文集. 457-462 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] N.Kogure, N.Sugino, and A.Nishihara: "DSP Memory Allocation Method for Indirect Addressing with Wide Range Update Operation by Multiple Registers" Proc.of 1998 IEEE Asia Pacific Conference on Circuits and Systems. 435-438 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 杉野 暢彦, 西原 明法: "モジュロー更新を考慮した間接アドレッシングのためのメモリ配置方法" 第12回ディジタル信号処理シンポジウム講演論文集. 633-638 (1997)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] N.Sugino, S.Miyazaki, and A.Nishihara: "DSP Code Optimization Methods utilizing Addressing Operations at the Codes without Memory Accesses" IEICE Trans.Fundamentals. E80-A,12. 2562-2571 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N.Kogura, N.Sugino, and A.Nishihara: "Memory Allocation Method for Indirect Addressing DSPs with *2 Update Operations" IEICE Trans.Fundamentals. E81-A,3. 420-428 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N.Sugino, and A.Nishihara: "Memory Allocation Methods for a DSP with Indirect Addressing Modes and their Application to Compilers" Proceedings 1996 International Symposium on Circuits and Systems. 2585-2588 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N.Kogura, N.Sugino, and A.Nishihara: "Memory Allocation Method for Indirect Addressing With Address Register Update Operations Within *2" Proceedings of the 10th Karuizawa Workshop on Circuits and Systems. 403-408 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N.Kogura, N.Sugino, and A.Nishihara: "Memory Address Allocation Method for a DSP with *2 Update Operations in Indirect Addressing" Proc.of the European Conference on Circuit Theory and Design. 1446-1459 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N.Sugino, and A.Nishihara: "Memory Allocation Method for Indirect Addressing with Modulo Update Operation" Proceedings of 12th Digital Signal Processing Symposium. 633-638 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N.Kogura, N.Sugino, and A.Nishihara: "DSP Memory Allocation Method for Indirect Addressing by Multiple Registers with Large Update Range" Proceedings of the 11th Karuizawa Workshop on Circuits and Systems. 457-462 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] N.Kogura, N.Sugino, and A.Nishihara: "DSP Memory Allocation Method for Indirect Addressing with Wide Range Update Operation by Multiple Registers" Proceedings of 1998 IEEE Asia Pacific Conference on Circuits and Systems. 435-438 (1998)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 1999-12-08  

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