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1999 Fiscal Year Final Research Report Summary

Research on the Hardware Mechanism to Assist Software based Caohe Coherence Schemes

Research Project

Project/Area Number 09680334
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionKYOTO UNIVERSITY

Principal Investigator

MORI Shin-ichiro  Kyoto University, Graduate School of Informatics, Associate, Professor, 情報学研究科, 助教授 (20243058)

Co-Investigator(Kenkyū-buntansha) GOSHIMA Masahiro  Kyoto University, Graduate School of Informatics, Research, Associate, 情報学研究科, 助手 (90283639)
Project Period (FY) 1997 – 1999
KeywordsDistributed Shared Memory / Cache / Coherency Controll / Parallel Processing / Network Computer / NCC-NUMA / CC-NUMA / Self Cleanup Cache
Research Abstract

In order to investigate the essential ability of the Non-Cache-Coherent NUMA system configured with write-back cache, we assumed an NCC-NUMA Architecture configured with Self-Cleanup Cache, which has an ability to enforce the write back of unused dirty line without invalidating the line, and evaluated its performance by simulation works.
The result of the simulation showed that 1) NCC-NUMA System can achieve comparable performance to CC-NUMA system if some moderate optimizations are forced to the application program, 2) NCC-NUMA System outperforms CC-NUMA System if the network latency arrives to the order of 100 processor cycle, and 3) the performance gain of NCC-NUMA System to CC-NUMA System increases with the increase of the network latency for the well optimized application programs.
We also found that, however, for some programs which were optimized to increase the memory access locality with the techniques like privatization or blocking, the self-invalidation and the self-cleanup of shared data placed in the local memory have a possibility of affecting the performance.
To deal with this problem, we have proposed the Self-Cleanup Cache with 2bit Directory Scheme. By configuring a 2bit directory with each local memory and maintain the local caching status, intra-node cache coherence in this system is maintained like the other directory based system, so that unnecessary invalidations and self-cleanups of locally cached data disappear. After further study of this scheme, we found that the Self-Cleanup Cache with 2bit Directory Scheme is well applicable to the SMP Cluster system, which adopts the one-chip multiprocessor in particular.

  • Research Products

    (8 results)

All Other

All Publications (8 results)

  • [Publications] 五島正裕: "超並列計算機Jump-1における分散共有メモリ管理とその性能評価"並列処理シンポジウム JSPP2000. (採録決定). (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 森眞一郎: "並列計算機アーキテクトからみた計算機クラスタ"情報処理. 39・11. 1078-1077 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 森眞一郎: "Optimized Code Generation for Heterogeneous Computing Environment Using Parallelizing Compiler TINDAR"Proc.of Parallel Architecture and Compilation Technique. 426-433 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 五島正裕: "Intelligent Cache Controller of a Massively Parallel Processor JUMP-1"Proc.of Int'l Workshop on Innovative Architecture for Future Generation High-Performance Proccesors and Systems. 116-124 (1997)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Masahiro Goshima: "Design of the Distributed Shared Memory Management for Massively Parallel Processor JUMP-1 and its Evaluation"Proc. of the Joint Symp. on Parallel Processing. (Accepted).

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shin-ichiro Mori: "Introduction to Computer Cluster-A Parallel Computer Architect's View-"IPSJ Magazine,. Vol.39, No.11. 1073-1077 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shin-ichiro Mori: "Optimized Code Generation for Heterogeneous Computing Enviroment using Parallelizing Compiler TINPAR"Proc. of Parallel Architectures and Compilation Techniques. 426-433 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Masahiro Goshima: "Intelligent Cache Controller of a Massively Parallel Processor JUMP-1"Proc. of Intn'l Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems,. 116-124 (1997)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 2001-10-23  

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