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1999 Fiscal Year Final Research Report Summary

Study of the implementation method for Newral Network Argoritm with a Multi-Context Dynamically Reconfigurable FPGA

Research Project

Project/Area Number 09680338
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionOsaka University

Principal Investigator

KITAMICHI Junji  Graduate School of Engineering Science, Osaka University, Tutor, 情報処理教育センター, 講師 (20234271)

Co-Investigator(Kenkyū-buntansha) HIGASHINO Teruo  Graduate School of Engineering Science, Osaka University, Professor, 大学院・基礎工学研究科, 教授 (80173144)
FUNABIKI Nobuo  Graduate School of Engineering Science, Osaka University, Assistant Professor, 大学院・基礎工学研究科, 助教授 (70263225)
Project Period (FY) 1997 – 1999
KeywordsDynamically Reconfigurable Logic / Multi Context / FPGA / Simulated Annealing / Greedy / Partition / CAD / Neural Network
Research Abstract

In this study, We propose an implementation method of a Multi-Context Dynamically Reconfigurable FPGA and a CAD algorithm for optimal use of it. Multi-Context Dynamically Reconfigurable FPGA is a VLSI which can be programmed during system operation with better reconfiguration time-efficiency than conventional Reconfigurable FPGA. We evaluated the hardware cost to add the Multi-Context Dynamically Reconfigurable FPGA by the result of synthesis of the hardware description of the Multi-Context Dynamically Reconfigurable FPGA. And We also evaluated the improvement of CLB (Configurable Logic Block) or bus usage by the implementation of the Neural Network Algorithm compared with conventional Reconfigurable FPGA. The CAD algorithm for Multi-Context FPGA minimizes reconfiguration time overhead proportional to the amount of the reconfiguration data. It inputs a finite state machine and outputs subsets of states called pages which is a reconfiguration unit of Multi-Context FPGA. The performance of the proposed algorithm is demonstrated experimentally.

  • Research Products

    (14 results)

All Other

All Publications (14 results)

  • [Publications] 馬場孝之,船曳信生,西川清史,由雄宏明: "マキシマム・ニューラルネットワークによる無線通信網の通信経路選択法の提案"電気学会論文誌C. vol.117-C no.7. 874-880 (1997)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 馬場孝之,船曳信生,西川清史: "マルチキャスト・パケット交換方式におけるワンショットスケジューリング問題のニューラルネットワーク解法"電子情報通信学会論文誌A. vol.J80-A no.11. 1973-1981 (1997)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 竹中要一,船曳信生,西川清史: "N-Queen問題を対象としたマキシマムニューロンモデルの競合解消方式の提案"情報処理学会論文誌. vol.38 no.11. 1242-1248 (1997)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Nobuo Funabiki, Makiko Yoda, Junji Kitamichi, and Seishi Nishikawa: "A gradual neural network approach for FPGA segmented channel routing problems"IEEE Transactions on Systems, Man, and Cybernetics. vol.29 no.4. 481-489 (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 糸将之,北道淳司,船曳信生: "動的再構成可能FPGAの設計とそれへの並列アルゴリズムの実装"情報処理学会研究報告. 98-DA-88. 1-8 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 江川晋爾,黒田映史,北道淳司,船曳信生: "FPGA配線問題に対する貧欲法とニューラルネットワークを併用した3段階アルゴリズムの提案"電子情報通信学会技術研究報告. CPSY98-90. 69-75 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 糸 将之: "マルチコンテキスト型動的再構成可能FPGAの一実現法とページ分割アルゴリズムの提案"平成10年度大阪大学大学院基礎工学研究科博士前期課程学位論文. (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 本多 亮: "マルチコンテキスト型動的再構成可能FPGAにおけるコンテキスト分割問題に対するGreedyおよびBilliardsアルゴリズムの提案"平成11年度大阪大学基礎工学部特別研究報告. (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Takayuki Baba, Nobuo Funabiki, Seishi Nishikawa, and Hiroaki Yoshio: "A maximum neural network algorith for route selection problems in multihop radio networks"Transactions IEE of Japan. vol.117-C, no.7. 874-880 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Nobuo Funabiki, Makiko Yoda, Junji Kitamichi, and Seishi Nishikawa: "A gradual neural network approach for FPGA segmented channel routing problems"IEEE Transactions on Systems, Man, and Cybernetics. vol.29, no.4. 481-489 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Masayuki Ito, Junji Kitamichi, and Nobuo Funabiki: "A Design of Dynamically Reconfigurable FPGA and An Implementation of Parallel Algorithm on it"IPSJ SIG Notes. 98-DA-88. 1-8 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shinji Egawa, Eiji Kurada, Junji Kitamichi, and Nobuo Funabiki: "A proposal of a three-stage greedy neural-network algorithm for FPGA routing problems"IEICE Technical Report. CPSY98-90. 69-75 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Masayuki Ito: "A Proposal of an Implementation method of a Multi-Context FPGA and its Page Partitioning Algorithm"Osaka University Master Thesis. (1999)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Ryou Honda: "A Proposal of Greedy and Billiards Algorithm for Context Partitioning Problem of Multi-Context FPGA"Osaka University Bachelor Thesis. (2000)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 2001-10-23  

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