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1998 Fiscal Year Final Research Report Summary

Hardware syntesis from formal descriptions of communication prorocols

Research Project

Project/Area Number 09680339
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionOsaka University

Principal Investigator

TANIGUCHI Kenichi  Osaka University, Graduate School of Enginireing Science, Department of Informatics and Mathematical Science, Professor, 大学院・基礎工学研究科, 教授 (00029513)

Co-Investigator(Kenkyū-buntansha) MORIOKA Sumio  IBM,Tokyo Research Institute, Researcher, 東京基礎研究所, 研究員
KITAJIMA Akira  Osaka University, Graduate School of Engineering Science, Department of Informat, 基礎工学研究科, 助手 (00304030)
OKANO Kozo  Osaka University, Graduate School of Engineering Science, Department of Informat, 基礎工学研究科, 助手 (70252632)
KITAMICHI Junji  Osaka University, Graduate School of Engineering Science, Department of Informat, 基礎工学研究科, 助手 (20234271)
HIGASHINO Teruo  Osaka University, Graduate School of Engineering Science, Department of Informat, 基礎工学研究科, 助教授 (80173144)
Project Period (FY) 1997 – 1998
KeywordsProtocol / Hardware design / Automatic curcuit synthesis / Register transfer level / High level synthesis / multi-rendezvous / VHDL / FDT
Research Abstract

In this research, we propose a technique for hardware implementation of protocol specifications in LOTOS.For the purpose, we define a new model called synchronous EFSMs consisting of concurrent EFSMs and a finite set of multi-redezvous indications among their subsets, and propose a conversion algorithm from a subset of LOTOS.The derived synchronous EFSMs described in VHDL can be easily implemented as a synchronous sequential circuit where all the modules corresponding to the EFSMs work synchronously with the same clock.By applying our technique to the Abracadabra protocol and a sinple network switch, it is confirmed that the derived circuit handles multi-rendezvous efficiently.

  • Research Products

    (6 results)

All Other

All Publications (6 results)

  • [Publications] 北嶋,安本,東野,谷口: "Method to Convert Concurrent EFSMs with Multi-Rendezvous into Synchronous Sequential Circuit" 電子情報通信学会英論文誌. Vol.E81-A-4. 566-575 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 安本,北嶋,東野,谷口: "Hardware synthesis from protocol specifications in LOTOS" Proc.of Joint Int.Conf.on 11th Formal Description Techniques and 18th Protocol Specification,Testing,and Verification (FORTE/PSTV '98). 405-420 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 北嶋,安本,東野,谷口: "Deriving Concurrent Synchronous EFSMs from Protocol Specifications in LOTOS" 電子情報通信学会英論文誌(A). (採録決定).

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Akira Kitajima, Keiichi Yasumoto, Teruo Higashino and Kenichi Taniguchi: "Method to Convert Concurrent EFSMs with Multi-Rendezvous into Synchronous Sequential Circuit" Trans.of IEICE. Vol.E81-A,No.4. 566-575 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Akira Kitajima, Keiichi Yasumoto, Teruo Higashino and Keiichi Taniguchi: "Deriving Concurrent Synchronous EFSMs from Protocol Specifications in LOTOS" Trans.of IEICE. Vol.E82-A,No.3.(to appear). (1999)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Kiichi Yasumoto, Akira Kitajima, Teruo Higashino and Kenichi Taniguchi: "Hardware synthesis from protocol specifications in LOTOS" Proc.of FORTE/PSTV'98. 405-420 (1998)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 1999-12-08  

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