1998 Fiscal Year Final Research Report Summary
Hardware syntesis from formal descriptions of communication prorocols
| Project/Area Number |
09680339
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | Osaka University |
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Principal Investigator |
TANIGUCHI Kenichi Osaka University, Graduate School of Enginireing Science, Department of Informatics and Mathematical Science, Professor, 大学院・基礎工学研究科, 教授 (00029513)
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| Co-Investigator(Kenkyū-buntansha) |
MORIOKA Sumio IBM,Tokyo Research Institute, Researcher, 東京基礎研究所, 研究員
KITAJIMA Akira Osaka University, Graduate School of Engineering Science, Department of Informat, 基礎工学研究科, 助手 (00304030)
OKANO Kozo Osaka University, Graduate School of Engineering Science, Department of Informat, 基礎工学研究科, 助手 (70252632)
KITAMICHI Junji Osaka University, Graduate School of Engineering Science, Department of Informat, 基礎工学研究科, 助手 (20234271)
HIGASHINO Teruo Osaka University, Graduate School of Engineering Science, Department of Informat, 基礎工学研究科, 助教授 (80173144)
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| Project Period (FY) |
1997 – 1998
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| Keywords | Protocol / Hardware design / Automatic curcuit synthesis / Register transfer level / High level synthesis / multi-rendezvous / VHDL / FDT |
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| Research Abstract |
In this research, we propose a technique for hardware implementation of protocol specifications in LOTOS.For the purpose, we define a new model called synchronous EFSMs consisting of concurrent EFSMs and a finite set of multi-redezvous indications among their subsets, and propose a conversion algorithm from a subset of LOTOS.The derived synchronous EFSMs described in VHDL can be easily implemented as a synchronous sequential circuit where all the modules corresponding to the EFSMs work synchronously with the same clock.By applying our technique to the Abracadabra protocol and a sinple network switch, it is confirmed that the derived circuit handles multi-rendezvous efficiently.
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