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1999 Fiscal Year Final Research Report Summary

Metal-substrate SOI integrated circuits technologies for 10GHz clock operation

Research Project

Project/Area Number 10305022
Research Category

Grant-in-Aid for Scientific Research (A)

Allocation TypeSingle-year Grants
Section一般
Research Field Electronic materials/Electric materials
Research InstitutionTOHOKU UNIVERSITY

Principal Investigator

OHMI Tadahiro  New Industry Creation Hatchery Center, Tohoku University, Professor, 未来科学技術共同研究センター, 教授 (20016463)

Co-Investigator(Kenkyū-buntansha) HIRAYAMA Masaki  Graduate School of Engineering, Tohoku University, Research Associate, 大学院・工学研究科, 助手 (70250701)
Project Period (FY) 1998 – 1999
Keywordsgas isolated interconnect / metal gate / high-permittivity gate insulator / metal-substrate SOI
Research Abstract

The purpose of this research project is to develop an ideal device structure for use in ultra-fast and ultra-high-density integrated circuit, I.e., gas isolated interconnect structure, metal-gate, high-permittivity gate insulator, metal-substrate SOI CMOS LSI. These technologies will increase integrated circuits operating frequency up to 20 GHz although 1 GHz was recognized as the upper limit in the present technology. In order to establish this device structure as industrial products, we have developed several excellent technologies based on the ultraclean processing concept, as follows :
I) Low-temperature Si epitaxial growth technology, II) Kr/OィイD22ィエD2 low-temperature oxidation technology, III) SiィイD23ィエD2NィイD24ィエD2 gate dielectric formation technology by microwave excited high-density plasma, IV) Low-temperature ultra-shallow source/drain junction formation technology, V) Low-resistivity bcc-phase Ta gate electrode formation technology by Xe plasma sputtering, VI) Giant-grain copper interconnects technology using TaNィイD22ィエD2 diffusion barrier layer, VII) Low-resistivity tantalum-silicided junction formation technology using Si-encapsulated silicidation technique, VIII) characterization technique of electrically active interface defects for SOI MOS device.
These results lead not only to the realization of ultrahigh-speed devices but also to the establishment of a number of advanced processing technologies which certainly will become the main stream in microelectronics in sub-100 nm era, impacting greatly the semiconductor manufacturing technology in future.

  • Research Products

    (12 results)

All Other

All Publications (12 results)

  • [Publications] T.Ohmi: "Improvement of Gate Reliability for Tantalum-Gate MOS Devices Using Xenon Plasma Sputteving Technology"IEEE Trans.on Electron Devices. 45. 2349-2354 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] T.Ohmi: "Minimization of BF_2^- implantation dose to reduce the annealing time for ultra-shallow source/drain junction formation below 600℃"Jpn.J.Appl.Phys.. 37. 1166-1170 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] T.Ohmi: "Enhancement of silicon epitaxy by increased phosphorus concentration in a low-energy ion bombardment process"Jpn.J.Appl.Phys.. 37. 3268-3271 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] T.Ohmi: "Formation of Ultra-Shallow and Low-reverse-bias-current Tantalum-silicided Junctions Using a Si-Ea capsulated Silicidation Techniyus"Jpn.J.Appl.Phys.. 87. 4277-4283 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] T.Ohmi: "Thin and Low-Resistivity Tantalum Nitvide Diffusion Barries and Giant-Grain Copper Infferconnect for Advanced ULSI Metallization"Jpn.J.Appl.Phys.. 38. 2401-2405 (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] T.Ohmi: "Gate Oxide Reliability Concerns in Gate-Metal Sputtering Deposition Process : An Effect of Low-Energy Large-Mass ion Bombardment"Microelectronics Reliability. 39. 327-332 (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] T. Ohmi: "Improvement of Gate Oxide Reliability for Tantalum-Gate MOS Devices Using Xenon Plasma Sputtering Technology"IEEE Trans. On Electron Devices. Vol. 45, No. 11. 2349-2354 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Ohmi: "Minimization of BFィイD22ィエD2 implantation dose to reduce the annealing time for ultra-shallow source/drain junction formation below 600℃"Jpn. J. Appl. Phys.. Vo. 37, No. 3B. 1166-1170 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Ohmi: "Enhancement of silicon epitaxy by increased phosphorus concentration in a low-energy ion bombardment process"Jpn. J. Appl. Phys.. 3268-3271 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Ohmi: "Formation of Ultra-Shallow and Low-reverse-Bias-Current Tantalum-silicided junctions Using a Si-Encapsulated Silicidation Technique"Jpn. J. Appl. Phys.. Vol. 87, Part 1, No. 8. 4277-4283 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Ohmi: "Thin and Low-Resistivity Tantalum Nitride Diffusion Barrier and Giant-Grain Copper Interconnects for Advanced ULSI Metallization"Jpn. J. Appl. Phys.. Vol. 3, Part 1, No. 4B. 2401-2405 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] T. Ohmi: "Gate Oxide Reliability Concerns in Gate-Metal Sputtering Deposition Process : and Effect of Low-Energy Large-Mass Ion Bombardment"Microelectronics Reliability. Vol. 39, No. 3. 327-332 (1999)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 2001-10-23  

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