1999 Fiscal Year Final Research Report Summary
Research on Intelligent Design Verification of VLSIs
| Project/Area Number |
10355014
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | The University of Tokyo |
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Principal Investigator |
ASADA Kunihiro VLSI Design and Education Center, The University of Tokyo, Professor, 大規模集積システム設計教育研究センター, 教授 (70142239)
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| Co-Investigator(Kenkyū-buntansha) |
IKEDA Makoto VLSI Design and Education Center, The University of Tokyo, Lecturer, 大規模集積システム設計教育研究センター, 講師 (00282682)
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| Project Period (FY) |
1998 – 1999
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| Keywords | VLSI / Power supply lines / Design rule / Power line noise / voltage sampler / Voltage scan-path / short / open |
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| Research Abstract |
We have been focusing on an intelligent design verification method, that can be applicable to chip fabrication services of VLSI Design and Education Center (VDEC) . Conventionally, layout verification has been based on pattern processing. It is , however, intelligent layout verification method, which is equivalent to that of expert designers is necessary for beginners' skill up along with design quality enhancement.
In this research, we have focused on designs and quality of power supply lines. We extract power lines from layout and estimate maximum current of lines based on transistor sizes connected to them. Current concentration and power line noise are derived from the maximum current and are reported to designers. To achieve this, we have examined real-time measurement technique of on-chip power line noise. We employed on-chip voltage monitor based on a voltage sampler with a regenerative comparator using a modified switched capacitor circuit technology. The resolutions in time and voltage are about 1[ns] and 20[mV] for a standard O.6um CMOS technology. We have fabricated test chips with the voltage monitors and load cells for emulating function blocks and demonstrated that above voltage monitor is effectively measure power supply bounce. We have proposed "on-chip Voltage scan-path technique" for monitoring real-time power bounce on chip. The voltage scan-path technique consists of voltage monitors connected serially as shift-register manner, which is just similar to boundary scan-path technique. Using this technique, power bounce in every major position of power lines can be monitored with only limited IO pins. This technique is expected to be necessary for failure analysis of denser LSls in near future.
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