1999 Fiscal Year Final Research Report Summary
Single-electron device based on the majority logic.
| Project/Area Number |
10450129
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | HOKKAIDO UNIVERSITY |
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Principal Investigator |
AMEMIYA Yoshihito Hokkaido Univ., Grad. School of Eng., Prof., 大学院・工学研究科, 教授 (80250489)
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| Co-Investigator(Kenkyū-buntansha) |
ASAI Tetsuya Hokkaido Univ., Grad. School of Eng., Inst., 大学院・工学研究科, 助手 (00312380)
AKAZAWA Masamichi Hokkaido Univ., Grad. School of Eng., Asso. Prof., 大学院・工学研究科, 助教授 (30212400)
YHO Kanji Hokkaido Univ., Research Center of IOE, Prof., 量子界面エレクトロニクス研究センター, 教授 (60220539)
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| Project Period (FY) |
1998 – 1999
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| Keywords | majority logic / single electron / tunnel / digital circuit / gate circuit |
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| Research Abstract |
In this project, we developed single-electron gate circuits based on the principle of the majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. It accepts an odd number of inputs and produces the corresponding output on the basis of the principle of majority decision; it produces an output of logic "1" if the majority of the inputs is 1 , and an output of "0" if the majority is 0. By combining the proposed majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation error induced by thermal agitation is also estimated.
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