1999 Fiscal Year Final Research Report Summary
Investigation of high performance three-dimensional integrated circuits using three dimensional MOS devices
| Project/Area Number |
10555112
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | TOHOKU UNIVERSITY |
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Principal Investigator |
ENDOH Tetsuo Research Institute of Electrical Communication, Tohoku University, Assistant Professor, 電気通信研究所, 助教授 (00271990)
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| Co-Investigator(Kenkyū-buntansha) |
SAKURABA Hiroshi Research Institute of Electrical Communication, Tohoku University, Research Associate, 電気通信研究所, 助手 (60241527)
MASUOKA Fujio Research Institute of Electrical Communication, Tohoku University, Professor, 電気通信研究所, 教授 (50270822)
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| Project Period (FY) |
1998 – 1999
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| Keywords | MOS transistor / Three dimensional MOS transistor / SGT / Three dimensional integrated circuit |
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| Research Abstract |
(1) Design and fabrication of SGT-type three-dimensional MOS transistor and its basic circuits.
The design system for the elementary three-dimensional transistor and three dimensional circuit were set-up and calibrated. The process flow to make the designed SGT type three dimensional MOS transistor and the elementary three-dimensional circuits were established.
(2) Clarifying the specific design parameters for the three-dimensional integrated circuit.
Evaluation system for three dimensional integrated circuit was constructed. By using this system, the SGT type three-dimensional MOS transistor and the elemental three dimensional circuit were evaluated. As a result of this evaluation, the specific design parameters for three-dimensional circuit was clarified.
(3) Proposal of a high packing density three dimensional memory
The Stacked Surrounding Gate Transistor (S-SGT)DRAM is proposed as a high packing density three-dimensional memory structure, according to the design rule for proposed three dimensional integrated circuit. This memory was structured by stacking several SGT-type cells in series vertically. S-SGT DRAM was realized by new three-dimensional stacking memory array technologies. It was clarified that the S-SGT DRAM which had the 4 stacking cells can achieve the cell size of 1.44FィイD12ィエD1 where the conventional DRAM can realize the 12FィイD12ィエD1.
(4) Design investigation of a high packing density three dimensional memory
S-SGT DRAM process design was proposed and a cell size of 2.4FィイD12ィエD1 was realized.
(5) Summary
In summary, the above given investigations resulted in a systematic, clarification of the basic design rule of SGT and of the corresponding three-dimensional integrated circuit architecture.
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Research Products
(2 results)
