1999 Fiscal Year Final Research Report Summary
Research on iterative decoding of product code composed of majority logic decodable codes.
| Project/Area Number |
10650356
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
情報通信工学
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| Research Institution | Nagaoka University of Technology |
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Principal Investigator |
OGIWARA Haruo Nagaoka University of Technology・Faculty of Engineering. Professor., 工学部, 教授 (30185532)
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| Co-Investigator(Kenkyū-buntansha) |
KOIKE Kiyoyuki Tokyo National Technical College. Lecturer., 講師 (20283038)
SHOHON Toshiyuki Nagaoka University of Technology・Faculty of Engineering. Research Associate., 工学部, 助手 (10242455)
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| Project Period (FY) |
1998 – 1999
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| Keywords | product code / majority logic / iterative decoding / turbo code / coded modulation / impulsive noise / inter-symbol interference |
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| Research Abstract |
A method to get weight distribution of a product code by using importance sampling is proposed. Performance of the code is predicted and the validity of it is shown by simulation.
Three types of simple decoding algorithm based on minimum reliability value is proposed. By comparing the results with those with the chase algorithm, performance is shown inferior within 1 dB and decoding speed is shown higher for a code with rate less than 45/63.
A hardware decoder based on the proposed algorithm is design by using FPGA. Scale of the hardware and decoding speed is discussed and necessary improvement is shown.
For a bursty impulsive noise channel, iterative decoding algorithm including noise state estimator is proposed for a block code and for a convolutional code. A performance evaluation method is proposed for a convolutional code.
For an impulsive noise channel, soft-decision feedback equalizer is proposed for a product code. For a convolutional code, an equlaization and decoding algorithm is derived based on a composite trellis of the code and the channel.
A iterative decoder for turbo trellis-coded modulation is designed with soft-output viterbi algorithm (SOVA) on a DSP. Since SOVA needs few multiplications, the ability of DSP is not fully used in the decoder.
An serially concatenated coded modulation is proposed and investigated for a comparison. Bit error rate of the proposed system is shown to decrease rapidly by increasing an interleave size.
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Research Products
(6 results)
