2000 Fiscal Year Final Research Report Summary
Studies on hardware algorithms for high-performance arithmetic circuits
| Project/Area Number |
10680349
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | Nagoya University |
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Principal Investigator |
TAKAGI Naofumi Nagoya University, Graduate School of Engineering, Professor, 工学研究科, 教授 (10171422)
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| Co-Investigator(Kenkyū-buntansha) |
TAKAGI Kazuyoshi Nagoya University, Graduate School of Engineering, Assistant Professor, 工学研究科, 講師 (70273844)
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| Project Period (FY) |
1998 – 2000
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| Keywords | arithmetic circuit / hardware algorithm / VLSI / Euclidean norm computation / cube rooting / powering / division in GF (2^m) / modular division |
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| Research Abstract |
1. We have developed a hardware algorithm for computing the Euclidean norm of a 3D vector which often appears in 3D computer graphics, and designed and implemented an LSI based on it.
2. We have developed a hardware algorithm for cube rooting which appears in computer graphics, and designed and implemented an LSI based on it.
3. We have developed a hardware algorithm for generating powers of an operand, such as recirocal, square root, reciprocal square root, reciprocal square, and so on, using a multiplier with operand modifier.
4. We have developed a hardware algorithm for addition under the assumption of left-to-righ input arrival, which is optimal in theory and very efficient in practice.
5. We have developed a hardware algorithms for modular division with very large modulus which is required in cryptosystems. It is based on the binay GCD algorithm.
6. We have developed a hardware algorithms for division in GF (2^m) which is required in coding and cryptosystems, and designed and implemented an LSI based on it. We have also developed a fast algorithms for multiplicative inversion in GF (2^m) based Fermar's theorem.
7. We have developed a fast addition algorithm on an elliptic curve over GF (2^n) using the projective coordinates which is required in public-key cryptosystems.
8. We have shown that the VLSI layout problem of a bit slice of an adder tree can be treated as the minimum cut linear arrangement problem of its corresponding p-q dag, and proposed two algorithms for minimum cut linear arrangement of p-q dags.
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