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2001 Fiscal Year Final Research Report Summary

Study on speculative parallel architecture using runtime program restructuring

Research Project

Project/Area Number 11480063
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionThe University of Tokyo

Principal Investigator

HIRAKI Kei  The University of Tokyo, Graduate School of Information Science and Technology, Professor, 大学院・情報理工学系研究科, 教授 (20238348)

Project Period (FY) 1999 – 2001
KeywordsSpeculative execution / automatic parallelization / program restructuring / Binary translation / thread-level parallel execution / speculative memory / simulation
Research Abstract

The speculative parallel architecture utilizing on-chip resources is proposed. The proposed architecture, Runtime Restructuring extracts parallelism dynamically at runtime from a sequential binary program. In order to reduce overheads associated with frequent fork/join and frequent register-to- register communication in existing thread-level speculative architecture, Runtime Restructuring modifies a sequential binary program to a speculative SPMD program with duplicated execution.
Since generation of control flow is influenced by the history of past execution, its parallelization is necessary to achieve the accurate execution status. Then we introduce a binary translation method to reduce overheads for analyzing parallel constructs and register dependency. We show the details of the parallel formation of control flow, and the evaluation results on SPEC benchmarks. Tomcatv gets 3.9 times and compress gets significant performance gain on 4CPUs. On SPEC INT benchmarks, binary translation is useful to reduce overheads in short loops.

  • Research Products

    (6 results)

All Other

All Publications (6 results)

  • [Publications] 中村 誠, 平木 敬: "二項順序関係により投機的メモリアクセスを制御するキャッシュシステム"電子情報通信学会技術報告(デザイン・ガイア). 42-5. 22-29 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 玉造 潤史, 平木 敬: "実行時プログラム再構成チップマルチプロセッサ"情報処理学会アーキテクチャ研究会研究報告. 10-23. 7-13 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] K.Hiraki et al.: "Data Reservoir : Utilization of Multi-Gigabit Backbone Network for Data-Intensive Research"Proc. SC2002. 1-10 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] M. Nakamura and K. Hiraki: "A cache memory system for speculative execution that utilize binary ordering relation"Technical Report of IEICE, CPSY. 45-2. 22-29 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] J. Tamatsukuri and K. Hiraki: "Architecture of chip multiprocessor with runtime program restructuring"Technical Report of IPSJ, ARC. 10-23. 7-13 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K. Hiraki et al.: "Data Reservoir : Utilization of Multi-Gigabit Backbone Network for Data-Intensive Research"Proc. SC2002, http://www.sc02.org. (2002)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 2004-04-14  

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