2001 Fiscal Year Final Research Report Summary
A study of Very-Large-Data-Path Architecture
| Project/Area Number |
11480066
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | The University of Tokyo |
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Principal Investigator |
TANAKA Hidehiko Graduate School of Information Science and Technology, The University of Tokyo, Professor, 大学院・情報理工学系研究科, 教授 (60011102)
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| Co-Investigator(Kenkyū-buntansha) |
SHIMIZU Shu Graduate School of Information Science and Technology, The University of Tokyo, Assistant, 大学院・情報理工学系研究科, 助手 (20011182)
SAKAI Shuichi Graduate School of Information Science and Technology, The University of Tokyo, Professor, 大学院・情報理工学系研究科, 教授 (50291290)
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| Project Period (FY) |
1999 – 2001
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| Keywords | VLDP Architecture / Computer Architecture / Micro Prosessor / Instruction-level parallerism / Speculative Execution / Multi-Path Execution / Branch Prediction / Value Prediction |
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| Research Abstract |
This fiscal year we decided upon the detailed specification of the Very Large Data Path (VLDP) architecture, and performed evaluation by the simulator. In order to raise fetch efficiency [that is one of the features of the VLDP architecture], the mechanism which changes dynamically the mode which fetches only a single path, and the mode which fetches two or more paths was proposed and were mounted in the simulator. About processing of load/store instructions during a different path, the conventional load store queue was divided, the technique of raising the scalability of mounting was proposed, and it mounted in the simulator. Multi path fetch, multi path management, a distributed register file, and a load store unit, ad other VLDP architecture modules were detailed, such as the signal line between each module, the timing of pipeline operation, the state transition, etc. were determined. Moreover, each module was unified and adjusted and it decided upon architecture specification. According to this specification, the VLDP integrated pipeline simulator (cycle based) was created. Moreover, decision of a instruction set, creation of a functional simulator, creation of a VLDP assembler, etc. performed maintenance of simulation environment. By the integrated simulator, we evaluate and toptimize the architecture.
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