| Co-Investigator(Kenkyū-buntansha) |
KANBARA Hiroyuki The Advanced Software Technology and Mechatronics Research Institute of Kyoto, Senior Researcher, エレクトロニクス室長
HASHIMOTO Masanori Graduate School of Informatics, Kyoto University, Research Associate, 情報学研究科, 助手 (80335207)
KOBAYASHI Kazutoshi Graduate School of Informatics, Kyoto University, Associate Professor, 情報学研究科, 助教授 (70252476)
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| Research Abstract |
With steady improvement in LSI fabrication technology, variabilities of device characteristics, which are caused by fluctuation of manufacturing conditions, affect circuit performance considerably. The variabilities of device characteristics can not be completely eliminated by tuning fabrication processes, and hence a new design optimization methodology that can fundamentally consider the variabilities is necessary.
In this research, we develop four methods as fundamental and application techniques to analyze and optimize circuit performance statistically; 1) a modeling technique of the variabilities of device characteristics, 2) a statistical performance analysis method and a circuit optimization technique for large analog circuits, 3) a worst-case analysis method for digital circuits, 4) a statistical static timing analysis method and a performance optimization technique.
1) We develop a transformation method from the variabilities of physical parameters to the variabilities of device
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characteristics using an intermediate model. We devise two models that represent the variabilities; one is for systematic variabilities on a wafer, and the other is for local random variabilities. We also develop a measurement method for both types of the variabilities.
2) As for statistical performance analysis for large analog circuits, we develop a method that links the device characteristics variabilities to the system-level performance variabilities. This method builds a response surface for each hierarchy, and links the derived response surfaces. With the modeling techniques of 1), we can obtain the relationship between the variabilities of physical parameters and the system-level performance variabilities. We also develop an yield optimization method for hierarchical top-down design style.
3) We develop a delay calculation model called vector synthesis model. This model can calculate practical worst-case delay time with small computational costs. We also devise a method that instantly derives vector synthesis models of large circuits looking up pre-characterized reference tables.
4) We develop a statistical static timing analysis method. This method treats the uncertainties in delay calculation as statistical variables, and the derives a probability distribution at every node in a circuit. We then obtain the probability distribution of the circuit delay. We also develop a performance optimization method that minimizes the worst-case delay. Less
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