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2001 Fiscal Year Final Research Report Summary

Self-Reconfigufation Architecture of Mesh-Connected Network for Multiprocessor Systems and The Implemantation

Research Project

Project/Area Number 11558032
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section展開研究
Research Field 計算機科学
Research InstitutionJapan Advanced Institute of Science and Technology

Principal Investigator

HORIGUCHI Susumu  Graduate School Information Science , Professor, 情報科学研究科, 教授 (60143012)

Co-Investigator(Kenkyū-buntansha) HAYASHI Ryouko  JAIST, Information Science, Research Associate, 情報科学研究科, 助手 (30303332)
YAMAMORI Kunihito  Miyazaki Univ, Faculty of Eng., Associate Prof., 工学部, 助教授 (50293395)
KOBAYASHI Hiroaki  Tohoku Univ, Information Center, Professor, 情報シナジーセンター, 教授 (40205480)
INOGUCHI Yasushi  JAIST, Information Center, Research Associate, 情報科学センター, 助手 (90293406)
Project Period (FY) 1999 – 2001
Keywordsfault tolerance / mesh array network / self-reconfiguration / wafer scale integration / FPGA
Research Abstract

This research deals with the issue of reconfiguring network interconnection for mesh-connected processor arrays (mesh array) implemented in VLSI/WSI. For massively parallel systems, it is becoming necessary to develop self-reconfiguratopn architecture that can automatically reconfigure partially faulty systems. Many reconfiguration algorithms have been proposed to date, however, most of them are not suitable for the self-reconfiguration and little literature shows the hardware implementation of the architecture actually. In this research, we propose a hardware-oiented self- reconfiguration architecture based on simple schemes of column bypass and south directional rerouting, and show a hardware implementation of proposed architecture using FPGA. The main feature of the proposed self-reconfiguration architecture is that faulty processors are avoided by switchig mechanisum, which can be determined its desired function automatically using states of neighboring processors. Simulated result shows that the proposed self-reconfiguration architecture is that faulty processors are avoided by switching machanism, which can be determined its desired function automatically using states of neighboring processors. Simulated result shows that the proposed architecture achieves higher system yield than those of the previous archtectures in rectangular mesh arrays. We also implement the reconfiguration system in FPGA and have been discussed in performance of it. The hardware overhead of redundant circuits such as switches and control circuits shows less than 4 %, where hardware cost of a procesor, which includes a test circuit, is 50 Kgates.

  • Research Products

    (14 results)

All Other

All Publications (14 results)

  • [Publications] Xiaohong Jiang, S.Horiguchi: "A New Framework for Critical Area Estimate in VLSI"Journal of Systems and Architecture. (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Xiaohong Jiang, S.Horiguchi: "Statistical Skew Modeling and Clock Period Optimization of Wafer Scale H-tree Clock Distribution Network"IEICE Trans. on Information and Systems. E84-D, No.11. 1476-1485 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Xiaohong Jiang, S.Horiguchi: "Statistical skew modeling for general clock distribution networks in presence of process variations"IEEE Trans. VLSI Systems. Vol.9, No.5. 704-717 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] X.Jiang, M.R.Khandker, S.Horiguchi: "Nonblocking Optical MINs Under Crosstalk-free Constraint"2001 IEEE Workshop on High Performance Switching and Routing. 307-311 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Y.Inoguchi, T.Matsuzawa, S.Horiguchi: "Cooling Scheme for 3D Stacked Mesh Array by Biased Shifting"Proc of IEEE High Performance Computing in Asia Conference. Goldcoast, Australia. 1-8 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] X.Jiang, M.R.Khandker, S.Horiguchi: "Upperbound for Blocking Probabilities of a Class of Optical MINs Under Crosstalk-free Constraint"2001 IEEE Workshop on High Performance Switching and Routing. 203-207 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] J.C.Lo, S.Horigudhi, edited: "Proc. the IEEE International Symposium on Defect and Fault Tolerance in VLSI System"IEEE Computer Society Press, ISBN 0-7695-0719-0(2001 Oct.). 500 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] X. Jtang, Y. Hao and S. Horigiichi: "A New fralnework for Criticial Area Estimate in VLSI^<II>"Journal of Systems and Architecture. To apear.

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] X. Jiang and S. Horiguchi: "^<II>Statistical Skew Modeling and Clock Period Optimization of Wafer Scale H-tree Clock Distribution network^<II>"IEICE Trans. On Information and Systems. vol. E84-D, No. 11. 1476-1485 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] X. H. Jiang and S. Horiguchi: "^<II>Statistical Skew Modeling for General Glock Distribution Networks in Presence of Process Variations^<II>"IEEE Trans. VLSI Systems. vol. 9, No. 5. 704-717 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Md. Mamun-ur-Rashid Khandker, X. Jiang, H. Shen and S. Horiguchi: "^<II>A New Architecture for Nonblocking Optical Switch Networks^<II>"Photonic Network Communications USA.. Vol. 3, No. 4. 393-400 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Y. Miura, S. Horiguchi and, V, K. Jain: "^<II>Deadlock-free Routing of Hierachical Interconnection Network : TESH (in Japanese)^<II>"Journal of Information Processing of Japan. Vol. 41, No. 5. 1370-1378 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] M. Kawai, Y. Inoguchi and S. Horigucih: "^<II>Deadlock-Free Routing of SRT Interconection Network for Massively Parallel Computers (in Japanese)^<II>"Journal of Information Processing of Japan. Vol. 41, Vol. 41, No. 5. 1370-1378 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] M. Kawai, Y. Inoguchi and S. Horiguchi: "^<II>Adaptive Routing of SRT Interconnection Network for Massively Parallel Computers (in Japanese)^<II>"Journal of Information Processing of Japan. Vol. 41, No. 7. 2010-2017 (2000)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 2003-09-17  

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