2001 Fiscal Year Final Research Report Summary
Fabrication of NbTiN Tunnel Junctions for Superconducting Logic Circuits
| Project/Area Number |
11650313
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | Saitama University |
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Principal Investigator |
MYOREN Hiroaki Saitama University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (20219827)
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| Co-Investigator(Kenkyū-buntansha) |
TAKADA Susumu Saitama University, Faculty of Engineering, Professor, 工学部, 教授 (80282424)
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| Project Period (FY) |
1999 – 2001
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| Keywords | NbTiN / Superconducting Tunnel Junctions / Dc Magnetron Sputtering / Single Flux Quantum Logic Circuits / Superconducting Circuits / NAND Gate / NOR Gate |
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| Research Abstract |
We prepared Nb_<1-x>Ti_xN (NbTiN) thin films by reactive do magnetron sputtering without intentional heating. Superconducting properties were strongly related to sputtering conditions. Lattice parameters of NbTiN films approached that of bulk NbTiN with decreasing the N_2 mole fraction in Ar and N_2 sputtering gas mixture. The film orientation was also strongly related with the sputtering conditions such as gas pressure. NbN thin films could grow epitaxially on MgO(100) substrates and showed very smooth surfaces. We found that smooth NbTiN films could be obtained on MgO(100) substrates with epitaxially grown NbN template layer. Superconducting critical temperature of NbTiN films were up to 14.5 K.
We prepared AlN thin films for tunnel barriers and found that smooth AlN thin layers could be obtained by reactive dc magnetron sputtering with relatively small sputtering power of 50 W. Etching rate of AlN layers was decreased with increasing CF_4 gas pressure and AlN layer could behave as a etching stopping layer. We fabricated NbTiN/AlN/NbTiN tunnel structure and observed I-V curves with the superoonducting energy-gap structure.
We successfully designed and fabricated single flux quantum (SFQ) NAND and NOR gates. We designed mask layouts of the gates assuming a 2.5 kA/cm^2 Nb/AlO_x/Nb junction process and optimized device parameters using an SFQ circuit-optimizing tool. Fabricated NAND and NOR gates had a critical margin more than ±20% for low-frequency operation. Bias margin for a fabricated NAND gate exceed ±25%.
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Research Products
(7 results)
