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2001 Fiscal Year Final Research Report Summary

A study on processing device for information coding of a nervous system

Research Project

Project/Area Number 11650355
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field 電子デバイス・機器工学
Research InstitutionNihon University

Principal Investigator

SEKINE Yoshifumi  Nihon University, College of Science & Technology, Professor, 理工学部, 教授 (90059965)

Co-Investigator(Kenkyū-buntansha) TAKAHASHI Sei  Nihon University, College of Science & Technology, Research Associate, 理工学部, 助手 (10256810)
SAEKI Katsutoshi  Nihon University, College of Science & Technology, Research Associate, 理工学部, 助手 (60256807)
Project Period (FY) 1999 – 2001
KeywordsNeuron Model / Neural Network / Neural Coding / Analog Circuit / Pulse-type / Axon Model / Lambda-type Neuron Model / Chaos Neuron Model
Research Abstract

We have been studying mechanisms of neural coding, and we have been trying to produce hardware from the viewpoint that development of new hardware neuron devices is one of the important problems in the study of neural networks. Furthermore, we have been studying how to develop a hardware neural network for information processing systems. In this study, we discuss as follows :
1. Investigate what happens neural coding in a nervous system.
2. Develop new neuron devices.
3. Develop temporal pattern recognition for neural network.
Results, 1. (1) It was shown that the asynchronous chaotic neuron model with effects on membrane potential on post synaptic potential had absolute refractoriness (References No. 1).
(2) The axon's output spike train displayed chaotic features when the chaotic spike train was transmitted by propagation along the active axon. Moreover, the time series intervals obtained from the axon's output spike train were an almost random train of the inter spike intervals (References No. 1).
2. (1) It was shown that the axon model, which has a certain threshold with respect to the signal height, exhibits the all-or-none law in the same way as the traditional active line, and also displays chaotic phenomena (References No. 3).
(2) We developed a pulse-type hardware bursting neuron device (References No. 4).
(3) We constructed pulse-type hardware neuron devices for neural networks (References No. 6, 7).
(4) We developed a pulse-type hardware bursting neuron device for IC implementation (References No. 9).
(5) We realized an asynchronous chaotic neuron device using analog circuits (References No. 8).
3. It was shown that by using a layered neural network, which has a structure suitable for a temporal nature, we investigated a new method of discriminating temporal patterns, such as EEG of a mouse. When we developed this neural network, we will be able to construct simple circuits, because there are not many connected lines among the neurons (References No. 5).

  • Research Products

    (24 results)

All Other

All Publications (24 results)

  • [Publications] 関根好文: "PSPの膜電位依存性を導入した非同期カオスニューロンモデル"電子情報通信学会(A). Vol.J82-A, no.9. 1489-1491 (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 染谷和孝: "軸索のハードウェアモデル"電子情報通信学会(C-II). Vol.J82-C-II, no.12. 655-661 (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 染谷和孝: "軸索のカオス伝達特性"電子情報通信学会(D-II). Vol.J83-D-II, no.3. 1015-1023 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 佐伯勝敏: "パルス形ハードウェアバーストニューロンモデル"電子情報通信学会(C). Vol.J83-C, no.3. 213-219 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 高橋 聖: "時系列パターン識別モデルのハードウェア化のためのニューラルネットアーキテクチャ"電子情報通信学会論文誌(D-II). Vol.J84-D-II, no.1. 170-177 (2001)

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      「研究成果報告書概要(和文)」より
  • [Publications] 関根好文: "CMOSによる八木型ハードウェアニューロンモデル"電子情報通信学会論文誌C. Vol.J84-C, no.6. 487-493 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 関根好文: "エンハンスメント型MOSFETによる∧形ニューロンモデル"電子情報通信学会論文誌C. Vol.J84-C, no.10. 984-994 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Jun Matsuoka: "Analog Hardware Implementation of a Mathematical Model of an Asynchronous Chaotic Neuron"IEICE Trans.Fundamentals. Vol.E85-A, no.2. 389-394 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 佐伯勝敏: "エンハンスメント型MOSFETを用いたパルス形バーストニューロンモデル"電子情報通信学会論文誌C. Vol.J85-C, no.3. 174-180 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 関根好文: "パルス形ハードウェアニューロンモデル"サイエンス社. 7 (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 関根好文: "非線形電子回路の解析技術とその応用"社団法人電気学会. 58 (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Katsutoshi Saeki: "Chaos in a Pulse-type Hardware Neuron Model"World Scientific Publishing Co. 19 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Y. Sekine: "Asynchronous Chaotic Neuron Model with Effects of Membrane Potential on Post Synaptic Potential"IEICE Trans. A. Vol. J82-A, no. 9. 1489-1491 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K. Someya: "Hardware of an Active Axon"IEICE Trans. C-II. Vol. J82-C-II, no. 12. 655-661 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K. Someya: "Transmission Characteristics for Chaotic Pulses along an Active Axon"IEICE Trans. D-II. Vol. J82-D-II, no. 3. 1015-1023 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K. Saeki: "Rulse-type Hardware Bursting Neuron Model"IEICE Trans. C. Vol. J83-C-II, no. 3. 213-219 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] S. Takahashi: "A Neural Net Architecture for Hardware Implemenation of Temporal Pattern Discrimination"IEICE Trans. D-II. Vol. J84-D-II, no. 1. 170-177 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Y. Sekine: "Yagi-Type Hardware Neuron Model with CMOS"IEICE Trans. C. Vol. J84-C, no. 6. 487-493 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Y. Sekine: "A Λ-Type Neuron Model Using Enhancement-Mode MOSFETs"IEICE Trans. C. Vol. J84-C, no. 10. 988-994 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] J. Matsuoka: "Analog Hardware Implementation of a Mathematical Model of an Asynchronous Chaotic Neuron"IEICE Trans. Fundamentals. Vol. E85-A, no. 2. 389-394 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K. Saeki: "Pulse-type Bursting Neuron Model, Using Enhancement Mode MOSFETs"IEICE Trans. C. Vol. J85-C, no. 3. (2002)

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      「研究成果報告書概要(欧文)」より
  • [Publications] Y. Sekine: "Pulse-Type Hardware Neuron Model"Science-sya. (1999)

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      「研究成果報告書概要(欧文)」より
  • [Publications] Y. Sekine: "Analysis Technique and Its Application of Nonlinear Electric Circuit"IEEJ. (1999)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K. Saeki: "Chaos in a Pulse-type Hardware Neuron Model"World Scientific Publishing Co.. (2002)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 2003-09-17  

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